 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ZR36057 DATA SHEET ENHANCED PCI BUS MULTIMEDIA CONTROLLER FEATURES T T T T T T T T Glueless interface to PCI bus (PCI spec. 2.1 compliant). Minimum interface to JPEG decoders (e.g. ZR36050 & ZR36016), MPEG1 decoders (e.g., ZR36110), video digitizers (e.g., SAA7110, SAA7111) and video encoders (e.g., SAA7188, MD207). Bi-directional DMA transfer of compressed data up to 11M bytes/sec. DMA transfer of video and overlay information. Support for fast still image compression and decompression. Smooth image down-scaler (up to 5-tap horizontal filter). On-chip pixel accurate masking. YUV-to-RGB converter with quantization noise reduction by error diffusion. T T T T T T T T T Video output: 15- and 16-bit RGB pixel formats, as well as 24-bit (packed and unpacked), and YUV 4:2:2. Hardware support for non-contiguous JPEG code buffers. Graceful recovery from extreme bus latencies both on video and code transfers. Choice of emulated interlaced video display, or single field display, to eliminate motion artifacts. Hardware support for simple, cost effective frame grabbing. I2C bus master port. Plug & Play support. 208-pin PQFP package. Accompanying software includes Video For Windows (VFW) drivers for Windows 3.1 and Windows 95. APPLICATIONS T T High quality video and audio capture/playback and editing boards for PCI systems. Multimedia/Graphics subsystems using a secondary PCI bus. T T PCI motherboards with multimedia capability. JPEG/MPEG1 solutions for PowerPC and Macintosh PCI systems. Video Decoder Video Encoder Audio Control Audio FIFO ZR36016 Strip Buffer 32kB SRAM Audio Codec Audio Core ZR36057 ZR36050 JPEG Core Graphics Sub-System PCI Bus Figure 1. Block Diagram of a Typical Motion JPEG System for PCI ZORAN Corporation T 2041 Mission College Blvd T Santa Clara, CA 95054 T (408) 986-1314 T FAX (408) 986-1240 August 1996 Enhanced PCI Bus Multimedia Controller Enhanced PCI Bus Multimedia Controller Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 The ZR36057 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 JPEG System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Motion Video Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Motion Video Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Still Image Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Still Image Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Notations and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Video Input Processor . . . . . . . . . . . . . . . . . . . . . . . 18 Horizontal Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Horizontal/Vertical Downscaler . . . . . . . . . . . . . . . . . . . . . .18 Color Space Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Video Output Control . . . . . . . . . . . . . . . . . . . . . . . . 19 Display Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Frame Grabbing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Output Pixel Organization . . . . . . . . . . . . . . . . . . . . . . . . . .19 Graphics Overlay. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JPEG Code Transfer . . . . . . . . . . . . . . . . . . . . . . . . . 20 The Code Buffer Table . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Fragment Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 JPEG Compression Modes . . . . . . . . . . . . . . . . . . . . . . . . .21 JPEG Decompression Modes. . . . . . . . . . . . . . . . . . . . . . .21 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Digital Video Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Digital Video Front End (VFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Video Input Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pixel Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 JPEG P_reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Video DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pixel Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Display Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Frame Grabbing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Overlay Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PCI Configuration Space Registers . . . . . . . . . . . . . 24 Application-Specific Registers (ASRs) . . . . . . . . . . 25 Video Front End Horizontal Configuration Register . . . . . .25 Video Front End Vertical Configuration Register. . . . . . . . .25 Video Front End, Scaler and Pixel Format Register . . . . . .26 Video Display "Top" Register . . . . . . . . . . . . . . . . . . . . . . .27 Video Display "Bottom" Register . . . . . . . . . . . . . . . . . . . . .27 Video Stride, Status and Frame Grab Register. . . . . . . . . .27 Video Display Configuration Register . . . . . . . . . . . . . . . . .27 Masking Map "Top" Register . . . . . . . . . . . . . . . . . . . . . . . .28 Masking Map "Bottom" Register . . . . . . . . . . . . . . . . . . . . .28 Overlay Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .28 System, PCI and General Purpose Pins Control Register .29 General Purpose Pins and GuestBus Control Register (I) .29 MPEG Code Source Address Register . . . . . . . . . . . . . . . .29 MPEG Code Transfer Control Register. . . . . . . . . . . . . . . .30 MPEG Code Memory Pointer Register . . . . . . . . . . . . . . . .31 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .31 I2C-Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 PostOffice Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 JPEG Mode and Control . . . . . . . . . . . . . . . . . . . . . . . . . . .33 JPEG Process Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Vertical Sync Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .34 Horizontal Sync Parameters . . . . . . . . . . . . . . . . . . . . . . . .34 Field Horizontal Active Portion . . . . . . . . . . . . . . . . . . . . . .34 Field Vertical Active Portion . . . . . . . . . . . . . . . . . . . . . . . .34 Field Process Parameters . . . . . . . . . . . . . . . . . . . . . . . . . .34 JPEG Code Base Address . . . . . . . . . . . . . . . . . . . . . . . . .34 JPEG Code FIFO Threshold . . . . . . . . . . . . . . . . . . . . . . . .34 JPEG Codec Guest ID . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 GuestBus Control Register (II) . . . . . . . . . . . . . . . . . . . . . .35 "Still Transfer" Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Host Control/Communication Services . . . . . . . . . . . . . . . . .9 Application-Specific Registers (ASRs) . . . . . . . . . . . . . . . . . . . . . 9 GuestBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PostOffice Handshaking Protocol . . . . . . . . . . . . . . . . . . . . . . . . . 9 Still Transfer Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interrupt Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Code DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 MPEG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 JPEG Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Digital Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Sampling The Incoming Video . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Synchronization Signal Generation . . . . . . . . . . . . . . . . . . . . . . . 11 ZR36057 Connection To The ZR36016 . . . . . . . . . . . . . . . . . . . 12 Pixel Transfer In Still Image Compression Mode . . . . . . . . . . . . 13 Pixel Transfer In Still Image Decompression Mode . . . . . . . . . . 13 GuestBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Flexible GuestBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Code-Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Doubleword to Bytes Mapping in Code-Write Operations. . . . . . 14 PostOffice Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 GuestBus Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PostOffice Handshaking Protocol . . . . . . . . . . . . . . . . . . . .15 Host Writes to a Guest Device . . . . . . . . . . . . . . . . . . . . . . . . . 15 Host Reads from a Guest Device . . . . . . . . . . . . . . . . . . . . . . . 15 Codec Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Compression Mode Code Transactions . . . . . . . . . . . . . . . . . . . 16 Decompression Mode Code Transactions . . . . . . . . . . . . . . . . . 16 Transaction Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Connecting The ZR36057 To The ZR36050. . . . . . . . . . . . . . . . 17 I2C Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . .17 Interrupt Requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 36 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . 36 2 Enhanced PCI Bus Multimedia Controller Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC Timing Specifications . . . . . . . . . . . . . . . . . . . . . 37 PCI Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Video Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 GuestBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Codec Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Appendix A: ZR36100 - ZR36057 Interface 44 ZR36100 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Mapping the ZR36100 on the ZR36057's GuestBus . . . . . . . 44 ZR36100 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 On-Line Commands and Status . . . . . . . . . . . . . . . . . . . . . . 44 Bitstream Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Appendix B: MD207/MD208 - ZR36057 Interface 45 MD207/208 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Mapping the MD207/208 on the ZR36057's GuestBus . . . . . 45 Sync Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Vertical Interpolation with the MD208 . . . . . . . . . . . . . . . . . . 45 Appendix C: Fitting the Input Size to the Required Display Window 46 Calculating the Horizontal Parameters:. . . . . . . . . . . . . . . . . . . . . . . . 47 Calculating the Vertical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3 Enhanced PCI Bus Multimedia Controller 1.0 INTRODUCTION 1.1 The ZR36057 The ZR36057 is a PCI adapter intended for multimedia applications on PCI systems. It supports high rate code (compressed data stream) transfer between the system memory and JPEG or MPEG processors. Simultaneously to the code transfer, the ZR36057 captures digital video, such as decompressed MJPEG (Motion JPEG), MPEG, or the output of a video digitizer/ decoder, and creates a scaled video window in the graphics display memory. The ZR36057 provides the host software with full control over a large number of non-PCI multimedia devices such as: ZR36050, ZR36016 (Zoran Motion JPEG Codec chip set), audio codecs, ZR36100/ZR36110 (Zoran MPEG decoders), etc, as well as any number of I2C devices, such us video digitizers, video encoders, etc. The ZR36057 interfaces directly to the PCI bus. As a bus master, it transfers data (e.g, MPEG or JPEG code) to or from the system memory, and writes digital video pixels to the graphics display memory. As a bus target, the ZR36057 reflects the host accesses onto a microcontroller-type 8-bit "Guest Bus". The ZR36057 has a special "Still Transfer" port by means of which the host software writes (or reads) digitized video, as RGB pixels, from the system memory to (or from) the video bus. This path enables fast transfer of still images to be compressed (or decompressed) by the JPEG chip set. for compression. The ZR36050 drives the code stream to the Codec Front End of the ZR36057, which transfers the compressed video fields using DMA to a system memory buffer allocated by the host. 1.2.2 Motion Video Decompression In Motion Video Decompression, the ZR36057 transfers the code stream from system memory via the ZR36057 Codec Front End to the ZR36050, using DMA. The ZR36050 decompresses the JPEG code and transfers the decompressed blocks to the ZR36016. The ZR36016 performs the block-to-raster conversion and drives the video to the video encoder to be displayed on a TV monitor. The ZR36016 video output is driven simultaneously to the Video Front End of the ZR36057 to be processed, as in the capture mode, and transferred using DMA to the PC display memory. 1.2.3 Still Image Compression In Still Image Compression mode an image bitmap is written by the host, pixel by pixel, through the PCI bus to the ZR36057. The ZR36057 transfers the pixels through its video bus port to the video input port of the ZR36016. After the first strip of 8 video lines is filled, the ZR36016 starts performing the raster-to-block operation, sending the blocks to the ZR36050. The ZR36057 generates and drives the required video synchronization signals for the ZR36016. The ZR36050 compresses the video blocks and drives the code stream to the ZR36057. The code stream is transferred using DMA to the host memory as in Motion Video Compression. 1.2 JPEG System Overview Figure 1 depicts an example of an MJPEG add-on board. The ZR36057 supports 4 basic JPEG modes of operation: * Motion Video Compression. * Motion Video Decompression. * Still Image Compression. * Still Image Decompression. 1.2.4 Still Image Decompression In Still Image Decompression mode, the ZR36057 fetches the code stream from system memory using DMA, as in Motion Video Decompression. The ZR36050 reads the compressed data from the ZR36057, decodes it and send the expanded blocks to the ZR36016, which drives the video to the video port of the ZR36057. From there the host software reads it out to system memory, pixel by pixel. Note that still image decompression can also be accomplished by configuring the ZR36057 in Motion Video Decompression mode, and transferring the decompressed video to a contiguous buffer in system memory instead of the display memory. Since this has a speed advantage over Still Image Decompression mode, it is the preferred method for most applications. 1.2.1 Motion Video Compression The video decoder directs the video in YUV 4:2:2 format, and the video synchronization signals, to the video input port of the ZR36016. The video is also transferred to the video encoder for display on a TV monitor and simultaneously to the Video Front End of the ZR36057. The ZR36057 can optionally down-scale the video, convert it to RGB, and transfer the pixels using DMA to the display memory of the host PC. In parallel, the ZR36016 performs the raster-to-block operation needed by the JPEG algorithm and transfers the video in block order to the ZR36050 4 Enhanced PCI Bus Multimedia Controller 1.2.5 Notations and Conventions External signals: Active-low mark [1]: Capital letters (e.g., IDSEL) Overbar (e.g., DEVSEL) capital (non-bold) letters (e.g., VFE) XXmsb_index..lsb_index (e.g., AD31..0) XXmsb_index:lsb_index (e.g., Mode27:16) R - read only RC - read-clear. Writing `1' clears the register bit. RS - read-set. Writing `1' sets the register bit to `1'. RW - read-write (contents of write can be read back) W - write only (contents of read are meaningless) Unmarked numbers are decimal (e.g., 365, 23.19). Hexadecimal numbers are marked with a `0x' prefix (e.g., 0xB000, 0x3). Binary numbers are marked with a `b' suffix (e.g., 010b, 0000110100011b). Internal function units: Buses: Register fields: Register types: Numbers: 1. In this document, an overbar is used to denote active low signals. In other documents referenced herein, such as the PCI specifications, the # suffix notation is often used instead. The two forms of notation are interchangeable. Thus, for example, DEVSEL is equivalent to DEVSEL#. 5 Enhanced PCI Bus Multimedia Controller 2.0 ARCHITECTURAL OVERVIEW The ZR36057 architecture contains two main data paths, the video path and the code path. The incoming video is processed along the video path and transferred to the graphics display memory using PCI DMA bursts. The ZR36057 Video Front End samples the video bus within a programmable active field window, defined with repect to the video synchronization signals. An optional vertical and horizontal smooth scale down can be applied, in order to support variable image sizes and variable PCI video data rate. The scaled video stream can be converted to various RGB formats. The converted pixels are packed and stored in a 256-byte Video FIFO, organized as 64 32-bit doublewords. The stored video pixels are read from the Video FIFO and transferred to the graphics display memory according to a display masking map controlled by and stored inside the ZR36057. The Code path is bidirectional. The data flow direction depends on the mode of operation. The code stream (MPEG or JPEG) is transferred between system memory and the internal Code FIFO of the ZR36057 using PCI DMA bursts. The ZR36057 controls the transfer and addressing in both directions. The Code FIFO size is 640 bytes, organized as 160 doublewords. In JPEG Compression modes the ZR36057 Codec Front End fills the Code FIFO. From the Code FIFO the code is transferred to the system memory, field by field. In JPEG Decompression modes the code stream flows in the opposite direction, from the system memory to the ZR36057 Code FIFO. The Codec Front End reads out the Code FIFO byte by byte onto the Code Bus. In MPEG Playback mode, the code stream is transferred to the ZR36057 Code FIFO from the system memory. The code bytes are read from the Code FIFO out to the Guest Bus. The ZR36057 video and the code paths operate simultaneously while the ZR36057 arbitrates the PCI bus requests for each process. Besides managing the Video and Code paths, the ZR36057 bridges the host CPU to peripheral devices (known as Guests). Using a dedicated handshaking mechanism (the "PostOffice" mechanism), host accesses to an internal ZR36057 register are reflected to the Guest Bus in order to enable indirect host read and write operations to the Guests. The ZR36057 contains a dedicated "Still Transfer" port which enables data flow between the PCI interface and the Video Front End. Using a specific handshake protocol, the host software may transfer digitized video (RGB pixels) from the system memory to the Video bus, and vice versa. This path enables very fast transfer of still video images to be compressed or decompressed by the JPEG codec. VCLK, VCLKx2 VSYNC, HSYNC FI RTBSY START, PXEN Y[7:0] UV[7:0] B[7:0] Video Front End (VFE) Video Input Processor Video DMA Controller Video FIFO GPIO[7:0] Application Specific Registers SCL SDA I2C Port GCS[7:0] GAD[2:0] GRD, GWR GRDY GWS GDAT[7:0] Guest Bus Master Code DMA Controller Code FIFO CEND CCS CBUSY CODE[7:0] GIRQ[1:0] Codec Front End (CFE) Interrupt Manager Figure 2. ZR36057 Block Diagram 6 PCI Interface Enhanced PCI Bus Multimedia Controller 3.0 PIN DESCRIPTIONS Symbol Type [1] Direction Description PCI Interface (48 pins) AD[31:0] C/BE[3:0] PAR FRAME TRDY IRDY STOP DEVSEL IDSEL REQ GNT PCICLK PCIRST INTA 3-state 3-state 3-state 3-state* 3-state* 3-state* 3-state* 3-state* I 3-state 3-state I I open drain I/O I/O I/O I/O I/O I/O I/O I/O I O I I I O Multiplexed address and data bus pins. Bus commands or byte enables. Even parity bit for AD31..0 and C/BE[3:0]. PCI cycle frame. PCI target ready indicator. PCI initiator ready. Indicates a target request to stop the current data transfer. PCI device select, indicates that the target has decoded its address. PCI initialization device select. Used as a chip-select to the ZR36057's configuration space. PCI bus request. PCI bus grant. PCI clock. PCI reset. When active, all ZR36057 output pins are tri-stated. A low to high transition puts the ZR36057 into its power-on reset state. Minimum active low duration is 3 PCI clocks. PCI interrupt request A. A low level on this signal requests an interrupt from the host. Digital Video Bus Interface (32 pins) Y[7:0]/R[7:0] UV[7:0]/G[7:0] B[7:0] VCLKx2 VCLK HSYNC VSYNC FI PXEN RTBSY START 3-state 3-state 3-state I I 3-state 3-state I O I O I/O I/O I/O I I I/O I/O I O I O Luminance/Red video lines. Chrominance/Green video lines. Blue video lines. Double frequency video bus clock. Digital video bus clock. Used as a qualifier to VCLKx2. Must be synchronized to VCLKx2. Digital video bus horizontal sync. Digital video bus vertical sync. Digital video bus field indicator (top/bottom). Active low Pixel Enable output to the ZR36016. Active low Strip Memory Overflow/Underflow signal from the ZR36016. Active high Start process output to the ZR36016. GuestBus Interface (25 pins) GCS[7:0] GADR[2:0] GDAT[7:0] GRD GWR GRDY GWS GIRQ[1:0] O O 3-state O O I I I O O I/O O O I I I Active low chip-select output to guest bus devices. Address outputs to guest bus devices. Guest data bus . Active low read output to guest bus devices. Active low write output to guest bus devices. Active high "guest ready" input. Guest Wait-State indication. Assertion of this active-low input allows the guest device to extend the GuestBus write (or read) cycle until it is capable of latching-in (or providing) the data. Positive-edge-sensitive interrupt request inputs from one or two of the guest bus slave devices. CodecBus Interface (11 pins) CODE[7:0] CEND CCS CBUSY 3-state I I O I/O I I O Code Bus connected to the ZR36050. Active low End of field process indication from the ZR36050. Active low Code Bus active cycle signal from the ZR36050. Active low Code FIFO Busy indication to the ZR36050. I2C bus data I2C Bus Interface (2 pins) SDA OD I/O 7 Enhanced PCI Bus Multimedia Controller 3.0 PIN DESCRIPTIONS (CONTINUED) Symbol SCL Type [1] OD Direction I/O Description I2C bus clock (qualifies for a single master operation only). General Purpose Programmable Inputs/Outputs (8 pins) GPIO[7:0] 3-state I/O General purpose input/output pins. After hardware or software reset all 8 pins are configured as inputs. Their logical levels are reflected as register bits. Any of the pins can be configured as output. In this state its logical level is driven by a register bit. These pins may be used to monitor or control various board-level functions. Test Pins (2 pin) ENID TEST Power (80 pins) GND VDD ground power Ground (50 pins). Power supply (5V) (30 pins). Test Test I I Used for IDD test. In normal operation must be connected to GND. Test pin used in test mode only. In normal operation must be connected to GND. 1. I - standard input-only * O - standard active driver * 3-state - bi-directional I/O pin * 3-state* - a special type of 3-state, as defined in the PCI spec. May be driven by only one PCI agent at any time * OD - open drain, may be shared by multiple drivers, as a wired-or. 4.0 FUNCTIONAL OVERVIEW The ZR36057 multimedia controller performs the following functions: * Interfacing to a YUV 4:2:2 digital video bus (e.g., Phillips SAA7110 or SAA7111). * Video DMA channel for burst transfers of video pixels. * Independent horizontal and vertical downscaling of the input image, with optional horizontal filtering. * Optional sync mastering with configurable HSYNC and VSYNC pulse widths and polarity. * Conversion of the YUV 4:2:2 digital video input into one of the following pixel formats: YUV 4:2:2, RGB 5,6,5, RGB 5,5,5 or RGB 8,8,8 (packed or unpacked). * Overlay support: any number of video pixels can be masked off, letting the corresponding graphics pixels appear instead of them. * Frame grabbing. * Two display modes: emulation of the interlaced input video, or a single field display. * Bidirectional Code DMA transfer with support for fragmented code buffers. * Control of the ZR36050/ZR36016 Motion JPEG chip set. The ZR36057 supports digital video in CCIR 601 or square pixel formats, following either the NTSC or PAL video standard. Other non-standard input schemes are supported as well. The functional description below follows the block diagram. 4.1 Digital Video Path 4.1.1 Digital Video Front End (VFE) The VFE samples the incoming YUV 4:2:2 video data and sync signals with a flexible sampling scheme, that makes it compatible with a wide variety of digital video sources. The digital input video can be cropped. The input resolutions supported by the VFE range from 32x32 to 1023x1023, in increments of one pixel. 4.1.2 Video Input Processor The chroma components of the video data are upsampled to YUV 4:4:4 format. All components are horizontally filtered. Five filtering schemes are implemented, with different parameters for chrominance and luminance samples. Horizontal and vertical downscaling is available if required. The vertical downscaling can be optimized for live video or Motion JPEG playback, in which each field is independent, or for the output of an MPEG-1 decoder such as the ZR36100 or ZR36110, which duplicates fields to produce its interlaced video output. 4.1.3 Pixel Formatting The filtered and scaled video is converted to the desired color space and packed according to the selected pixel format. YUV 4:2:2, 24-bit RGB (packed or unpacked) and 15- and 16-bit RGB are supported. An error diffusion algorithm can be applied to the RGB 5,5,5 and 5,6,5, in order to eliminate quantization artifacts on the output image. 4.2 Video DMA Controller 4.2.1 Pixel Bursts The packed pixels are transferred directly to the display memory (or to the system memory), using PCI DMA bursts. Both Little 8 Enhanced PCI Bus Multimedia Controller and "Gib" Endian formats are supported where applicable (Refer to the PCI Multimedia Design Guide, Revision 1.0). Compression (Decompression) mode. The Still Transfer port is mapped inside the ASR area, and a special controller interconnects this port to the ZR36057's extended video bus (24 bits RGB). The Still Transfer handshake protocol enables high rate pixels transfer between the system memory and the JPEG processor via the ZR36057. 4.2.2 Display Modes The display mode can be configured to either emulated interlaced video (both input fields are displayed simultaneously on the non-interlaced monitor) or single field display. The latter is appropriate for motion artifact elimination when displaying live or decompressed Motion JPEG video. 4.3.5 I2C Port A software-driven I2C port allows controlling of I2C devices. 4.2.3 Frame Grabbing The ZR36057 can grab video frames (scaled or non scaled), or fields, in any of the pixel formats listed above, directly into system memory, eliminating the need for memory on the add-in board. 4.3.6 Interrupt Manager Interrupt requests associated with several internal and external conditions are sent to the host via the PCI bus (using INTA). Selection of interrupt originators is programmable. 4.4 Code DMA Controller 4.2.4 Overlay Control Graphics overlay is supported, in that display memory areas that are "owned" by graphics applications, may not be loaded with video pixels, allowing true windowing and overlay. The software driver prepares a masking map of the video rectangle, and the ZR36057 uses this map for masking decision, when transferring the pixels to the display memory. The ZR36057 includes a DMA channel for transferring data between the system memory and a selected device on the Code Bus or GuestBus. Two configurations are supported: * MPEG mode. The data flow is unidirectional, from the system memory, to the ZR36057's GuestBus. * JPEG mode. The data flow is bidirectional, and the direction is determined by the selected sub-mode. In JPEG Compression, the data flows from the Codec bus to the system memory. In JPEG Decompression, the data flows from the system memory to the Codec bus. 4.3 Host Control/Communication Services 4.3.1 Application-Specific Registers (ASRs) The name "application-specific" distinguishes these registers from the PCI configuration space registers. These memory mapped registers provide the host software with full control over the operation of the ZR36057. The ZR36057 claims a contiguous space of 4 KBytes in system memory. 4.4.1 MPEG Mode In MPEG mode, the data flows from the system memory to the ZR36057's GuestBus. Typically, this would be a compressed bitstream, to be decompressed by a device such as an MPEG decoder attached to the GuestBus. Other examples are sampled audio (WAV data), MIDI token stream, etc. Temporary latencies on the PCI bus or the GuestBus are handled without loss of data. The GuestBus master simultaneously serves the PostOffice accesses and the code DMA transfers: DMA transfers are viewed as the "main" task of the GuestBus master, while any number of PostOffice requests may occasionally interrupt the DMA traffic. The DMA controller supports both auto-initialized (cyclic) block transfers, or single block transfers. The size of the destination block in main memory can be selected out of several possible sizes, ranging from 8 KBytes up to 256 KBytes. The destination block may also be virtually split into several sub-blocks, allowing the ZR36057 to interrupt the host when a sub-block has been transferred. This feature provides the software with a means of optimizing the refill accesses according to the application requirements and the disk performance. 4.3.2 GuestBus Host software control over non-PCI devices, such as a Motion JPEG codec, an MPEG decoder, a video encoder, etc., is done through the ZR36057's GuestBus. Host accesses to these "guest" devices, mapped as application specific registers inside the ZR36057, are output as GuestBus cycles. Such accesses can either use the PostOffice handshaking protocol, or the Code DMA Controller. The first method is adequate for commands, configuration data, etc., while the second method provides a faster channel, and is intended for continuous transfer of data such as a compressed bitstream. 4.3.3 PostOffice Handshaking Protocol The ZR36057 PostOffice handshaking protocol, implemented over the GuestBus, allows host accesses to relatively slow guest devices, with no degradation of the PCI bus performance. 4.3.4 Still Transfer Mechanism The ZR36057 supports a dedicated Still Transfer port, by means of which the host writes (reads) image pixels in JPEG Still Image 4.4.2 JPEG Modes In the JPEG modes, the data flows between the system memory and the ZR36057's Codec bus. In JPEG Compression, from the 9 Enhanced PCI Bus Multimedia Controller Codec bus to the system memory; in JPEG Decompression, from the system memory to the Codec bus. The JPEG code data inside the system memory is structured within code buffers. Each code buffer may contain a compressed field or a frame (2 fields), in accordance with a user configurable register bit. The ZR36057 supports four code buffers, defined dynamically in a dedicated table (the Code Buffer Table) in the system memory. The actual memory of each code buffer may be fragmented. The content of each entry in the code buffer table is a pointer to a secondary Fragment Table. The fragment table contains the pointers to the allocated memory chunks (fragments). In JPEG Compression mode, the host software builds and updates the code buffer table and the fragment tables according the memory allocated by the operating system. On every JPEG field/frame process, the ZR36057 Code DMA Controller reads the fragment table pointer of the current buffer from the code buffer table, and then fills up the buffer fragments one by one. In JPEG Decompression mode, the host software builds the code buffer table and fragment tables, and fills the fragments with the compressed field or frame. On every JPEG process, the ZR36057 Code DMA Controller retrieves the code fragments one by one, and directs them to the Codec bus. 5.0 INTERFACES 5.1 PCI Bus Interface In general, the ZR36057 is compatible with the PCI 2.1 specifications. As a bus master, it may initiate two types of data transfer over the PCI bus: * Memory Write (PCI command 0111b), from the ZR36057's Video FIFO buffer to the display memory (or main memory), and from ZR36057's Code FIFO buffer to the system memory. * Memory Read Line (PCI command 1110b), from system memory to the ZR36057's Mask Buffer[1] and from system memory to the ZR36057's Code FIFO buffer. As a bus target, the ZR36057 responds to the following types of transfer: Memory Read Memory Read Line Memory Read Multiple Memory Write Configuration Read Configuration Write (0110b) (1110b) (1100b) (0111b) (1010b) (1011b) The error reporting signals, SERR and PERR, are not included in the ZR36057: as a multimedia device it is only required to report parity errors through the PCI status register. The ZR36057 uses the INTA PCI interrupt request line. 5.2 Digital Video Interface The ZR36057 interfaces to a wide spectrum of digital video devices. The Video Interface is bidirectional and two video pixel flows are supported: * The incoming video is sampled and directed via the ZR36057's video input processor to the graphics display memory or system memory. * The video pixels are transferred to or from the system memory using a dedicated mechanism (the Still Transfer mechanism). The ZR36057 supports two sync signal source configuration options: * External sync - the sync signals are driven by the external video source. * Internal sync - the sync signals are generated internally and mastered by the ZR36057. All other PCI commands are ignored. Memory Read Line and Memory Read Multiple are handled exactly like Memory Read. Normally, as a slave, the ZR36057 is intended to be accessed with single data phase cycles. However, multiple phase bursts are supported. When the ZR36057 is accessed in a burst it increments its internal (offset) address such that each data phase is routed to/from the next address location (in doublewords). The ZR36057 supports byte enables, such that an access to explicit bytes is possible. In JPEG Motion Video Compression and Decompression modes as well as in MPEG mode, the Video Interface transfers the incoming video to the ZR36057's video input processor. The sampling of the video stream is performed according to the video clocks and sync signals. In JPEG Motion Video Compression mode and in MPEG mode, the synchronization source should be external. In JPEG Motion Video Decompression mode, the synchronization source can be either external or internal. In JPEG Still Image Compression and Decompression modes, the ZR36057 uses a dedicated mechanism (the Still Transfer mechanism) as a means for the host software to transfer pixels to or from the compression module. The Video Interface masters 1. Not shown in the block diagram. 10 Enhanced PCI Bus Multimedia Controller the extended 24-bit video bus and the synchronization signals in order to drive the pixels to the ZR36016 or get them from it, as appropriate. The following four subsections detail the four basic functions of the Video Interface: * Sampling the incoming video. * Generating the synchronization signals. * Pixel transfer in Still Image Compression. * Pixel transfer in Still Image Decompression. VSPol Table 1: Video Front-End Parameters Parameter HEnd ExtFI HSPol Description Number of pixel clocks in a line from the active edge of HSYNC until the last pixel to be sampled. This one bit parameter indicates whether the video source provides a field indication signal. The HSYNC polarity. HStart and HEnd are counted from the active edge of HSYNC. `1' means that HStart, HEnd will be counted from the negative edge of HSYNC. The VSYNC polarity. VSstart and VEnd are counted from the active edge of VSYNC. `1' means that VStart, VEnd will be counted from the negative edge of VSYNC. Top Field Interpretation. If field indication is derived from the FI input signal (see ExtFI), TopField indicates the interpretation of the FI signal: TopField=`1' - FI high indicates the top field (default value). TopField=`0' - FI low indicates the top field. If field indication is derived internally from HSYNC and VSYNC, TopField indicates the interpretation of the level of HSYNC as sampled by the active edge of VSYNC: TopField=`1' - HSYNC high indicates the top field (default value). TopField=`0' - HSYNC low indicates the top field. Polarity of VCLK as a data qualifier. If VCLKPol=1 the video input is sampled with those positive edges of VCLKx2 that correspond to VCLK=1. If VCLKPol=0, the video input is sampled by those positive edges of VCLKx2 that correspond to VCLK=0. 5.2.1 Sampling The Incoming Video The ZR36057's Video Front End (VFE) interfaces to a standard YUV 4:2:2 video bus. It samples the Y7..0, UV7..0, HSYNC and VSYNC with every other positive edge of VCLKx2. The valid positive edge (out of every two consecutive ones), which is the one used for sampling, is "marked" by VCLK, i.e., VCLK is used as a clock qualifier. The qualifying polarity of VCLK is configured by the host. This scheme makes the ZR36057 compatible with a wide range of digital video sources and immune to board-level parasitic delays. VCLKx2 (positive edges) is used internally in the video processing pipeline. The VFE generates a field indication signal targeted to some internal video processing units. There are two alternative ways of generating the field indication. With devices that output a field indication, the VFE uses the FI input as an indicator of the current field identity. The interpretation of the logical level of FI (top or bottom field) is configured by the host. With devices that do not provide such an indication, the VFE infers the field identity from the relationship of HSYNC to VSYNC. The VFE can capture square pixel and CCIR-601 formats, or user defined formats, within the limitation of its parameters. The maximum theoretical total input resolution is 1023 pixels/line x 1023 lines per frame. Cropping of the input image is possible by proper configuration of the VFE parameters. Table 1 lists the Video Front End parameters. The host software needs to configure these parameters according to the timing parameters of the video source (e.g., SAA7110, SAA7111, ZR36100, etc.) and the required cropping. Note that these parameters relate to the input video, and not to the destination video window. TopField VCLKPol 5.2.2 Synchronization Signal Generation The ZR36057 supports internal generation of the video synchronization signals. In this mode the ZR36057 generates and drives VSYNC and HSYNC signals.Using software programmable parameters, the ZR36057 can generate various video synchronization signal formats. Table 3 lists the sync signal parameters. The host software configures those parameters according the mode of operation and the video peripheral devices used. The polarity of the sync signals is determined by the VSPol and HSPol parameters (Table 2) Table 2: Synchronization Signal Parameters Table 1: Video Front-End Parameters Parameter VStart Description Number of lines (HSYNCs) from the active edge (positive or negative, according to VSPol) of VSYNC to the first line to be sampled. Number of pixel clocks in a line from the active edge of HSYNC until the first pixel to be sampled. Number of lines (HSYNCs) from the active edge (positive or negative, according to VSPol) of VSYNC to the last line to be sampled. Parameter FrmTot LineTot VsyncSize Hsync Start Meaning Total number of lines per frame (e.g., in NTSC: 525) Total number of pixel clocks per line (e.g., in CCIR NTSC: 858) The length of the VSYNC signal, measured in lines. The point in the scan line at which the HSYNC signal should be asserted. HStart VEnd 11 Enhanced PCI Bus Multimedia Controller The ZR36057 Video Interface drives out the video synchronization signals synchronized with the negative edge of VCLKx2 (every other edge). The VCLK input is used as a phase qualifier. The timing of the rising and the falling edges of VSYNC with respect to the HSYNC signal are: * Odd fields - The edges of VSYNC occur in the middle of the non-active portion of HSYNC. * Even fields - The edges of VSYNC occur in the middle of the active portion of HSYNC. source (such as the video decoder of Figure 1), and if necessary its sync signals, must be tri-stated using software control. In Still Image Decompression mode, the sync signals are driven by the ZR36057. Decompressed video is transferred from the ZR36016's PXOUT bus to the ZR36057's Video Interface. In this mode of operation, the video bus and sync signals of an external video source (such as the video decoder of Figure 1) must be tristated. Table 3 defines the ZR36016 and the ZR36057 parameters which define the portion of the field to be processed (the active portion) and the type of field to begin with. 5.2.3 ZR36057 Connection To The ZR36016 Figure 3 shows the recommended connections between the ZR36057 and the ZR36016. Table 3: Parameters Defining The Active Portion Of A Field Parameter Meaning The number of pixels to be skipped, counted from the active edge of HSYNC. The number of active pixels in a line. The number of lines to be skipped counted from the active edge of VSYNC. The number of active lines in a field. The type of the first field to be processed. `1' means an Odd field, `0' means an Even field. NAX PAX From External Video Source ZR36016 PXCLK SYSCLK VIN HIN PXIN[23:0] PXEN CBSY START PXOE PXOUT[23:0] VOUT HOUT DATA[7:0] ADD[1:0] CS RD WR RESET To Video Encoder VCLK ZR36057 NAY PAY Odd_Even VCLKx2 VSYNC HSYNC YUV[15:0]/RGB[23:0] PXEN RTBSY START GPOn 5.2.3.1 START Signal Control The START Signal is used in order to start the Compression/ Decompression process at the correct time for the desired field type. GDAT[7:0] GADD GCSn GRD GWR GPIOn 5.2.3.2 PXEN Signal Control The ZR36057 drives the PXEN input of the ZR36016. While PXEN is deactivated, the ZR36016 does not sample the PXIN bus, nor the HIN and VIN inputs. Also, it freezes the PXOUT bus, and HOUT and VOUT. In order to keep the ZR36057 and the ZR36016 synchronized, deactivation of PXEN by the ZR36057 also `holds' the horizontal counting and processing inside the ZR36057. In Motion Video Compression mode, PXEN is activated continuously. In Motion Video Decompression mode, PXEN is asserted by then ZR36057 after latching the rising edge of RTBSY, indicating that the first strip is ready in the ZR36016 strip memory. In Still Image Compression mode, the image is transferred to the ZR36057 by the host software pixel by pixel. PXEN is activated only when a pixel is ready to be sent out from the ZR36057 Video Interface to the ZR36016 video input. In Still Image Decompression mode, the image is read from the ZR36057 by the host software pixel by pixel. PXEN is activated to get the next pixel from the ZR36016 only after the previous pixel has been read by the host. Figure 3. Recommended ZR36057 to ZR36016 Connections In Motion Video Compression, the YUV video and synchronization signals are driven by the external video source (for example, a SAA7110) to the inputs of the ZR36057 and ZR36016. The ZR36057 disables the PXOUT bus of the ZR36016 by deasserting PXOE, in order to prevent bus contention. In Motion Video Decompression, the synchronization signals are driven by the ZR36057 (in sync master mode) or by an external sync generator, associated with the video source. The decompressed digital video is transferred from the ZR36016 PXOUT bus to the ZR36057 video interface. The video bus of the external video source, and if necessary its sync signals, must be `tri-stated' using software control. In Still Image Compression, the video bus as well as the sync signals are driven by the ZR36057. The ZR36057 deasserts the PXOE input of the ZR36016. The video bus of the external video 12 Enhanced PCI Bus Multimedia Controller PXEN can be de-asserted dynamically (in the middle of a process) in response to several different conditions. The dynamic de-assertion is enabled independently by three configuration bits - VFIFO_FB, CFIFO_FB, RTBSY_FB. The host software is allowed to set those bits only while the ZR36057 is the sync master. When VFIFO_FB is set, if the Video FIFO is close to overflow status, PXEN is de-asserted to hold the ZR36016 video output until the Video FIFO is emptied. When CFIFO_FB is set, if the Code FIFO underflows, and CBUSY is asserted, PXEN is deasserted to hold the ZR36016 video output until the Code FIFO is filled. When RTBSY_FB is set, if RTBSY is asserted by the ZR36016 during the active portion of the field, PXEN is deasserted until RTBSY is de-asserted. The Still Transfer write protocol and the associated internal mechanism of the ZR36057 are described below: * The host writes a pixel using a single data phase memory write cycle. The pixel is latched in the Still Transfer register using the PCI clock. * The Still_Bsy bit is set. * The incoming pixel is synchronized with the Video Interface clock. The PXEN output signal is asserted and the pixel is driven out on the correct video clock phase. * Feedback from the Video Interface resets the Still_Bsy bit, indicating that the video port is empty and the following host write is permitted. 5.2.5 Pixel Transfer In Still Image Decompression Mode The image is transferred from the ZR36057's extended 24-bit video bus to system memory. The host software reads the pixels one by one from the Still Transfer register. After each pixel is fetched from the video port, it is synchronized with the PCI clock, ready to be read by the software. Before each read access, the host software should check the Still_Bsy bit to verify availability of data in the register. The register contents are valid only if the Still_Bsy bit is 0. Note that by configuring the WaitState parameter, it is possible to ensure that the Still Transfer register will be valid every read access, making it unnecessary to check the Still_Bsy bit. The protocol for a still image decompression read operation, and the ZR36057's behavior, are as follows: * The ZR36057 checks the Still_Bsy bit. If it is 1, meaning that the previous valid pixel was read by the host, the ZR36057 fetches a new pixel from the ZR36016. * PXEN is asserted, causing a new pixel to be driven onto the video bus. * The new pixel is synchronized with the PCI clock and latched in the Still Transfer register. * Still_Bsy is reset to 0, to indicate that a new valid pixel is available. * The host software reads the pixel by means of a memory read access to the Still Transfer register, and Still_Bsy is set to 1. 5.2.3.3 RTBSY Signal Control The ZR36057's RTBSY input is connected to the ZR36016's CBSY output. The ZR36057 uses RTBSY to detect overflow and underflow conditions in the ZR36016 strip memory. In Motion Video Compression mode, RTBSY asserted at the trailing edge of HSYNC, which indicates a strip buffer overflow, stops the compression process for a field period until the beginning of the following field. In Motion Video Decompression mode, de-assertion of RTBSY is used to decide when to initiate the decompression process. In all modes, when RTBSY_FB is set, RTBSY is checked by the ZR36057 at the following times: * Before the trailing edge of VSYNC, which triggers the start of a new field process in the ZR36016, * During the active portion of the field. The ZR36057 de-asserts PXEN if RTBSY is asserted at those times. PXEN is asserted again after RTBSY is de-asserted. 5.2.4 Pixel Transfer In Still Image Compression Mode The image is transferred by the host software to the ZR36057's extended 24-bit video bus. The host writes the pixels one by one to a dedicated register (the Still Transfer register) in the ZR36057. Each pixel is synchronized with the video clock and transferred to the Video Interface port. Two modes of host access are supported: * The host verifies, by polling, the availability of the Still Transfer register before each pixel write access. Typically, this mode would be used after writing the first pixel of each line, before writing the remainder of the line. * The host configures the WaitState parameter and writes the pixels continuously to the Still Transfer register. The ZR36057 de-asserts the PCI TRDY signal every host access with the timing specified by the WaitState parameter. Typically, this mode would be used to transfer the pixels of a line after the first. 5.3 GuestBus Interface The ZR36057 masters a generic MCU-style bus intended to concurrently host up to eight slave devices (referred to as "guests"). The bus consists of 8 data lines (GDAT[7:0]), 3 address lines (GADR[2:0]), 8 active-low chip-select lines (GCS[7:0]), read and write signals (GRD, GWR), and a wait-state insertion line (GWS). The bus also includes two interrupt-request inputs (GIRQ[1:0]) and one status/acknowledge input (GRDY). Three types of data transfers are possible on the guest bus. One is a code-write cycle, initiated by the code DMA controller of the ZR36057, targeted to one of the guests, configured a priori for 13 Enhanced PCI Bus Multimedia Controller such write cycles [2] . The second is a GO command to the ZR36050 (configured a priori as one of the guests) in JPEG mode. The third is a PostOffice cycle, initiated by the host software, targeted to any one of the eight guests; in particular, PostOffice cycles are used to program the ZR36016 and ZR36050. register are also specified by the PostOffice register. In both read and write cycles the timing parameters of the cycle are those configured by the host for the targeted guest. Upon completion of a PostOffice cycle, the pending bit is reset to `0' by the ZR36057. PostOffice Write: The GuestBus master transfers the least significant 8 bits of the PostOffice register out on the bus. PostOffice Read: The GuestBus master reads from the specified target and writes the input byte into the least significant 8 bits of the PostOffice register (POData) 5.3.1 Flexible GuestBus Timing Different guest devices may have different bus timing requirements. In order to meet these requirements and still master the GuestBus efficiently, the ZR36057 has two timing parameters for each guest: TgdurN is the duration of a GWR or GRD signal when accessing guest N. TgrecN is the minimum recovery time in which GRD and GWR must be non active after the rising edge of the previous access (read or write) to guest N. Tgdur and Tgrec are configured by the host in units of PCI clock (3,4,12 or 15 PCI clocks are the possible values). Additional timing parameters are given in section 14.0 "AC Timing Specifications". 5.3.5 GuestBus Wait States 5.3.2 Code-Write Operations Code-Write cycles are initiated by the GuestBus master if all of the conditions below are met: * The CFIFO is not empty. * A PostOffice request is not pending. * The GRDY input is high (`1'). A code-write cycle consists of reading one code byte from the CFIFO and writing it to the guest selected by the host for codewrite cycles, to the register address configured by the host. The timing parameters of the code-write cycle are those programmed by the host for this specific guest device. Note that the same parameters apply for PostOffice accesses to this guest. Slow guests that are equipped with a "bus hold" output can force a code-write or PostOffice GuestBus cycle to be extended by one or more additional PCI clocks, by asserting the GWS signal right after the GuestBus master asserts the GRD or GWR signal. GWS is sampled with the PCI clock that follows the assertion of GWR or GRD. When GWS is sampled high again, the cycle is completed. If T gdur of the accessed guest has already expired since the assertion of GRD or GWR, the next PCI clock will latch the data (in case of a read) and GRD (or GWR) will be deasserted. The recovery portion of the cycle will then take place, and the cycle will be completed. Insertion of wait states is possible during both code-write and PostOffice cycles. The maximum number of PCI clock cycles allowed for GRD or GWR, including wait-states, is 64. If a guest holds the cycle until this limit expires, the GuestBus master aborts the cycle. If the cycle was a PostOffice one, the PostOffice time-out bit of the PostOffice register is set to `1', and the PostOffice pending bit is cleared. If the cycle was a code-write (or code-read, if viewed from the PCI side), the code-write time-out flag (CodTime) is set to `1'. Figure shows two examples of GuestBus cycles. The upper one is a write to guest 0, register 0, followed by a read from guest 0, register 5. Note that for guest 0 Tgdur0=3 and Tgrec0=4. The lower example shows a read from guest 2, register 1, with 3 wait-states inserted by the guest. Notice that the assertions of GADR and GCS are done together. The assertion of GRD and GWR is done one PCI clock after the assertion of GADR and GCS. The de-assertion of GRD and GWR is done one PCI clock before the de-assertion of GADR and GCS. 5.3.3 Doubleword to Bytes Mapping in Code-Write Operations The code is read in doublewords from main memory, and transferred in bytes to the guest device. The ordering of the bytes is such that the least significant byte of the doubleword is the first one to be sent over the GuestBus, and the most significant byte is the last one. 5.3.4 PostOffice Operations When the PostOffice pending bit (POPen) in the PostOffice register is set to `1', the GuestBus master completes the current code-write cycle (if such is executed), and executes a PostOffice cycle, even when the Code FIFO is not empty. The type of the cycle (read or write) is determined by the PostOffice direction bit (PODir). The identity of the targeted guest and its specific 2. A typical choice for guest configured a priori for the code-write cycles would be a decompression device, such as the ZR36100/ ZR36110, in the ZR36057's MPEG mode. 14 Enhanced PCI Bus Multimedia Controller 5.4 PostOffice Handshaking Protocol Reading data from or writing data to any of the ZR36057 guests using the PostOffice mechanism requires the host software to follow the handshaking protocol described below. The main idea is that the host has to poll the PostOffice request pending bit in order to confirm the availability of the GuestBus and verify the validity of the data contained in the PostOffice data byte. In general, host accesses to the PostOffice register may change the PostOffice pending bit, as explained below. Thus, the host software must ensure that accesses to the PostOffice register are governed by a central routine. For example, independent accesses to the PostOffice register both from an interrupt service routine and the main processor task(s), or from more than one task in a multitasking environment, might cause a deadlock, unless explicit protection measures are taken. identity (0,...,7), the specific guest register (0,...,7), and an indication that this is a write request (direction bit = 1). As a result of writing to the PostOffice data byte, the PostOffice pending bit is set to `1'. * The ZR36057 completes the current code-write cycle, if one is being executed, and, before executing the next code-write cycle (if one is needed), it executes the pending PostOffice request. At the completion of the GuestBus write cycle it clears the request pending bit. * The host may read the PostOffice register, to verify that the pending bit is `0', meaning that the write request has been completed. * Note that in multiple (back-to-back) PostOffice operations the host has to poll the request pending bit only once between two requests, since reading this bit zero indicates both that the previous request has been completed and that the next request can be made. 5.4.1 Host Writes to a Guest Device * The host reads the PostOffice register, and checks the PostOffice pending bit. If this bit is `1', the write cycle cannot be executed now, because the GuestBus master is busy executing a previous PostOffice read or write request. Once this bit is `0', the write request can be made. * The host writes a full doubleword to the PostOffice register, containing the data byte to be sent to the guest, the guest's 5.4.2 Host Reads from a Guest Device * The host reads the PostOffice register, and checks the PostOffice pending bit. If this bit is `1', the read cycle cannot be executed now, because the GuestBus master is busy executing a previous PostOffice read or write request. Once this bit is `0', the read request can be made. 1 PCI CLK GCS0 GADR[2:0] GWR GRD GWS GDAT[7:0] 2 3 4 5 6 7 8 9 10 11 12 13 0x0 0x5 Data valid from ZR36057 Data valid from Guest Example 1 1 PCI CLK GCS2 GADR[2:0] GWR GRD GWS GDAT[7:0] 2 3 4 5 6 7 8 9 10 11 12 13 0x1 Sampling Points Example 2 Figure 4. Two Examples of GuestBus Cycles 15 Enhanced PCI Bus Multimedia Controller * The host writes a full doubleword to the PostOffice register, containing the guest's identity (0,..,7), the specific guest register (0,...,7), and an indication that this is a read request (direction bit = 0). The data portion of the doubleword is meaningless, but should be set to a byte of zeros. As a result of writing to the PostOffice data byte, the PostOffice pending bit is set to `1'. * The ZR36057 completes the current code-write cycle, if one is being executed, and before executing the next code-write cycle (if one is needed), it executes the pending PostOffice request. It transfers the byte read from the guest to bits 7...0 of the PostOffice register. At the completion of the GuestBus read cycle it clears the request pending bit. * The host may read the PostOffice register, to verify that the pending bit is `0', meaning that the read request has been completed and the data portion of the PostOffice register is the result. * Note that in multiple (back-to-back) PostOffice operations the host has to poll the request pending bit only once between two requests, since reading this bit zero indicates both that the previous request has been completed and that the next request can be made. rising edge of VCLKx2. The ZR36057's Codec Interface samples the data with VCLKx2 enabled by CCS. VCLKx2 CCS CODE[2:0] (Input) n n+1 Figure 5. Compression Mode Code Transactions 5.5.2 Decompression Mode Code Transactions The functional timing diagram for decompression is shown in Figure 6. In this example, two code bytes are transferred from the ZR36057 to the ZR36050. The falling edge of CCS designates the start of the cycle. The data is driven by the ZR36057. The ZR36050 samples the data with the rising edge of COE (note that COE is not an input to the ZR36057; it is mentioned here only for the completeness of the description). VCLKx2 CCS COE (Not an Input to the ZR36057) 5.5 Codec Bus Interface The Codec Front End (CFE) interfaces to the ZR36050 JPEG Codec to transfer code (compressed data) to or from the ZR36057. The CFE is designed to operate with the ZR36050 configured in Code Bus Master mode. In Compression mode, the CFE receives the code stream from the codec and transfers it to the Code FIFO. In Decompression mode, the CFE transfers the code stream from the Code FIFO to the codec in response to the codec's read requests. The CFE uses the CODE[7..0] bus to transfer the code using the handshaking signals CCS and CBUSY, synchronized to VCLKx2. The ZR36057 supports the highest ZR36050 code bus transfer rate, one clock cycle per byte transfer (ZR36050 CFIS parameter = 0). CODE[2:0] (Output) n n+1 Figure 6. Decompression Mode Code Transactions 5.5.3 Transaction Termination The ZR36050 is the master of the code transactions in Compression and Decompression modes. Any number of bytes can be transferred in a contiguous burst transaction. The ZR36057 uses the ZR36050's CBUSY to block CODE bus transactions, in order to prevent overflow of the Code FIFO in compression or underflow in decompression. Figure 7 shows the functional timing diagram for CODE bus transaction termination. The ZR36050 examines CBUSY one clock cycle prior to the beginning of each access cycle. The ZR36057 asserts CBUSY one VCLKx2 cycle before the beginning of the last desired code transfer cycle. VCLKx2 CCS This access is blocked. 5.5.1 Compression Mode Code Transactions The functional timing diagram for compression is shown in Figure 5. In this example, two code bytes are transferred from the ZR36050 to the ZR36057. The falling edge of CCS designates the start of the cycle. The data is driven by the ZR36050 at the COE / CWE CODE[2:0] CBUSY Figure 7. Transaction Termination 16 Enhanced PCI Bus Multimedia Controller 5.5.4 Connecting The ZR36057 To The ZR36050 Figure 8 shows the recommended connection of the ZR36057 to the ZR36050. ZR36050 CLK_IN CCS CBUSY END CODE[7:0] ZR36057 VCLKx2 CCS CBUSY CEND CODE[7:0] In Motion Video Compression mode, the first GO command is initiated by the host after finishing the initialization of all the peripheral devices. After the first field, the GO command is executed after the code of the previous field has been transferred to the system memory. In Decompression mode, the GO command is executed only after the Code FIFO has been filled from the relevant system memory code buffer. Important Note: The automatic GO command is enabled by the Go_En register bit, in the JPEG Mode and Control Register. If the host software tries to execute a PostOffice cycle while Go_En is set to `1' (enabled), the PostOffice cycle may not be executed correctly. Therefore, Go_En must be disabled during PostOffice accesses. The following is the sequence of actions required for a Post Office access or series of accesses: * Disable the Go_En bit. * Wait at least 15 PCI clock cycles to allow the currently executing GO command, if there is one, to be completed. ADDR[9:0] DATA[7:0] CS RD WR RESET Register n+1 GADD GDAT[7:0] GCSn GRD GWR GPIOn Figure 8. ZR36057 to ZR36050 Connections n * Execute the PostOffice access, or the series of accesses. * Enable the Go_En bit (at least for 5 PCI clocks). If an internal GO command is requested while Go_En is disabled, it is stored internally, and executed when Go_En is enabled again. Note that there is a trade-off between the "chunk" size of a series of PostOffice accesses and the delay imposed on the ZR36050 GO command. Using a large chunk size reduces the overhead resulting from the need to toggle Go_En, but delaying the GO command too much can prevent the next field process from executing correctly. 5.5.4.1 ZR36050 Host Interface The host interface of the ZR36050 is controlled by the ZR36057 as one of the guests. The recommended guest timing parameters are Tdur=12, Trec=3. An external register must be added in order to support access to the entire ZR36050 internal memory space. This external register is controlled by the ZR36057 as an additional guest. One basic host access to the ZR36050 internal memory via the ZR36057 is performed using two successive guest bus accesses. The first is to the external address register during which the GDAT bus holds (for example) the 8 Lsb's of the ZR36050 internal memory address. The second is the command itself during which the GDAT bus holds the data to be written to the ZR36050 internal memory and the 2 Msb's of the address are driven by GADD[1..0]. 5.5.4.4 CCS Input Signal The ZR36050 CCS signal designates the start of a code transaction. It stays active until the end of the transaction. In Compression mode, the ZR36057 uses CCS to enable the sampling of the incoming code stream. In Decompression mode, it uses CCS to enable the drive of the code stream. 5.5.4.2 CEND Input Signal Assertion of END by the ZR36050 indicates the end of a field process in compression or decompression. This is latched as CEND in the Codec Interface. 5.6 I2C Bus Interface The I2C port of the ZR36057 consists of a clock signal, SCK, and data signal, SDA. Both have two possible levels: active low or passive tri-state. This configuration lets the ZR36057 be the only master of an I2C clock. Both lines must be pulled-up externally. By accessing the I2C application-specific register bits appropriately, the host software can generate valid I2C start and stop conditions, write address and write or read data one bit at a time. 5.5.4.3 The ZR36050 GO Command The GO command signals the ZR36050 to start a compression or decompression process. The GO command is performed automatically by the ZR36057, by writing to address 0x00h of the ZR36050 internal memory. The host software is responsible for pre-loading this address to the external address register after the completion of ZR36050 initialization. The ZR36057 uses the JPEGuestID and the JPEGuestReg parameters for the GO command guest address. 5.7 General Purpose I/O Pins The ZR36057 has 8 general purpose I/O pins, fully controlled by the host. Each of these pins can be separately configured as 17 Enhanced PCI Bus Multimedia Controller input or output. When configured as an output, the host is able to force the level of a pin through its corresponding register bit. Each one of these events can be separately enabled or disabled through the corresponding bit in the Interrupt Control Register. An additional global enable bit enables or disables all interrupts. When an interrupt-associated event occurs, two things happen: * The corresponding bit in the Interrupt Status Register is set. * If the interrupt is enabled, and the interrupts are enabled globally, then the INTA open-drain output pin is asserted to its active-low level. Both the status bit(s) and INTA remain active, until the host clears those status bits that are currently set. This is done by writing a `1' to those bits. When the host does that, the INTA output signal returns to its passive, tri-state level. If the host attempts to clear any of the Interrupt Status Register bits at the same time that the interrupt logic attempts to set it (because of an interrupt event), the set operation has priority over the clear operation. 5.8 Interrupt Requests The ZR36057's interrupt manager connects to the various conditions that may generate an interrupt request, enables or disables them as specified in the Interrupt Control Register, and drives the INTA output. It stores the corresponding status bits in the Interrupt Status Register, and clears the status bits per host instructions. The ZR36057 can associate any one of the following events with an interrupt request: * A positive edge on the GIRQ1 input pin. * A positive edge on the GIRQ0 input pin. * MPEG mode - the code memory buffer pointer passing one of its report points. * JPEG modes - successful completion of a JPEG field or frame process (in compression or decompression). 6.0 VIDEO INPUT PROCESSOR 6.1 Horizontal Filter Prior to a significant horizontal down scaling of the input image, it is advisable to apply one of the possible horizontal filters. The filter type is selected through the HFilter parameter. HFilter = 0 HFilter = 1 HFilter = 2 HFilter = 3 HFilter = 4 Filter 1: No luminance filter, 3-tap pre-interpolation filter of chrominance. Filter 2: 3-tap luminance filter, 3-tap pre-interpolation chrominance filter. Filter 3: 4-tap luminance filter, 4-tap chrominance filter. Filter 4: 5-tap luminance filter, 4-tap chrominance filter. Filter 5: 4-tap luminance filter, 4-tap chrominance filter. The vertical downscaler can operate in two ways. If DupFld=0 it treats the top and bottom fields the same way. If DupFld=1 it uses different line dropping topologies for the top and the bottom fields, such that if the fields are equal (one field is actually duplicated, like the output of most MPEG-1 decoders), then the total loss of information is minimized. For example, when the video source is a video digitizer, it is recommended to apply DupFld=0, and when the video source is the ZR36110, and the CCIR size is down scaled by half or more, it is recommended to apply DupFld=1. 6.3 Color Space Converter The color space converter converts the YUV input to RGB format. The YUV2RGB parameter determines the type of conversion: YUV2RGB = 00b YUV2RGB = 01b YUV2RGB = 10b YUV2RGB = 11b no conversion, output format is YUV 422. conversion to RGB 8,8,8 (24-bit output) conversion to RGB 5,6,5 (16-bit) conversion to RGB 5,5,5 (15-bit) 6.2 Horizontal/Vertical Downscaler The horizontal and vertical down scalers are independent of each other. The horizontal scaling ratio is configured through the HorDcm parameter. HorDcm indicates the number of pixels to drop out of every 64 consecutive pixels. HorDcm ranges from 0 to 63, where 0 represents the no scaling configuration (1:1 input to output ratio). The vertical scaling ratio is configured through the VerDcm parameter. VerDcm indicates the number of lines to drop out of every 64 consecutive lines. VerDcm ranges from 0 to 63, where 0 represents the no scaling configuration (1:1 input to output ratio). When the 15- or 16-bit RGB format is selected, it is advisable to apply the error diffusion option, in order to eliminate false contours from the output image. This option is selected by the ErrDif parameter (1 turns the error diffusion option on, while 0 turns it off). 18 Enhanced PCI Bus Multimedia Controller 7.0 VIDEO OUTPUT CONTROL The ZR36057 outputs the video pixels over the PCI bus, using DMA bursts, initiated and controlled by the ZR36057's Video DMA Controller. In order to enable the DMA Controller, the Master Enable bit of the PCI configuration space must be set to `1', and the VidEn bit in the Video Display Configuration Register must also be set to `1'. Once VidEn=='1', the software is not allowed to change registered parameters that are involved in the video processing. The register description (See "ApplicationSpecific Registers (ASRs)" on page 25) specifies the conditions under which each parameter is allowed to be modified. The ZR36057 transfers the video to a rectangle in the display (or system) memory, defined by a base address for each field (MaskTopBase, MaskBotBase), an inter-line stride (DispStride), and the rectangle height (VidWinHt) and width (VidWinWid). Obviously, these parameters must be provided by the host prior to enabling the Video DMA Controller. also given a new value. If needed, other video parameters can be changed now, e.g., pixel format, etc. * The host sets FrameGrab=1. The ZR36057 waits until the next VSYNC and then transmits two consecutive fields to main memory. * After the second of the two fields is completed, FrameGrab is cleared by the ZR36057. * When the host senses (after constant polling or polling inside VSYNC-triggered interrupts) that FrameGrab=0 again, it sets the old addresses back to VidTopBase and VidBotBase. DispStride is given back its old value. The remainder of the previous video parameters can be restored now. * The host sets SnapShot=0, putting the ZR36057 back into the continuous video display mode. * With the next VSYNC the ZR36057's Video DMA Controller resumes "normal" live display operation. 7.1 Display Modes The ZR36057 can either display both fields, emulating the interlaced input, or only the top field. The latter option has the advantage of reducing the motion artifacts that might be exhibited when interlaced video is diplayed on a non-interlaced monitor. The parameter that controls the display mode is DispMod. By a proper configuration of the display base addresses it is also possible to display two fields (from either one or two separate video sources) on two separate rectangles (video windows). 7.3 Output Pixel Organization The output pixel format is determined by the following parameters: YUV2RGB, Pack24 (applicable only to RGB 8,8,8 format), and LittleEndian (applicable to all formats, excluding the 24-bit packed). Following are the bit organizations of the different pixel formats when a video doubleword is transferred over the PCI bus: Table 4: YUV 4:2:2 Pixel Format Bits Endian-ness Little Endian 31...24 Y17...0 V07...0 23...16 V07...0 Y17...0 15...8 Y07...0 U07...0 7...0 U07...0 Y07...0 7.2 Frame Grabbing The ZR36057 has a special mode for capturing video frames (or fields) and storing them in system memory. This mode is invoked by setting the SnapShot parameter to `1'. When in this mode, every time the host switches the FrameGrab bit from `0' to `1', the ZR36057 downloads a frame (or a field, if DispMod==0), to memory. Following is an example of a flow of actions intended to grab one frame. The example assumes that the vertical sync is used as an interrupt source (by externally tying VSYNC to GIRQ0 or GIRQ1), and that prior to grabbing the frame, the ZR36057 operates in the "normal" continuous scheme of live video display. * Through a push-button click in the application GUI the user triggers a frame grabbing request. * The host sets SnapShot=1. The ZR36057's Video DMA Controller waits for the next VSYNC and then freezes the live display. Since now SnapShot=1 and FramGrab=0, video parameters can be changed (even without VidEn=0; refer to section 12.0 "Application-Specific Registers (ASRs)"). * The host sets new addresses in VidTopBase and VidBotBase. These addresses point to main memory. DispStride is Gib Endian Table 5: RGB 5,5,5 Pixel Format Bits Endian-ness Little Endian Gib Endian 31...24 0,R14...0, G14...3 G12...0, B14...0 23...16 G12...0, B14...0 0,R14...0, G14...3 15...8 0,R04...0, G04...3 G02...0, B04...0 7...0 G02...0, B04...0 0,R04...0, G04...3 Table 6: RGB 5,6,5 Pixel Format Bits Endian-ness Little Endian Gib Endian 31...24 R14...0, G15...3 G12...0, B14...0 23...16 G12...0, B14...0 R14...0, G15...3 15...8 R04...0, G05...3 G02...0, B04...0 7...0 G02...0, B04...0 R04...0, G05...3 19 Enhanced PCI Bus Multimedia Controller Table 7: 24-bit Unpacked Pixel Format Bits Endian-ness Little Endian Gib Endian 31...24 0x0 B7...0 23...16 R7...0 G7...0 15...8 G7...0 R7...0 7...0 B7...0 0x0 Bus Cycle First Second Third 31...24 B17...0 G27...0 R37...0 23...16 R07...0 B27...0 G37...0 In the 24-bit packed format the first active pixel in a line is always packed as indicated in the "First" row of Table 8. From then on the byte organization is as described by the table. Table 8: 24-bit Packed Pixel Format Bits 15...8 G07...0 R17...0 B37...0 7...0 B07...0 G17...0 R27...0 8.0 GRAPHICS OVERLAY The ZR36057's Video DMA Controller is capable of masking off (i.e., not transmitting) pixels that are marked by `0' in a masking map prepared and maintained by the driver software. The masking feature, referred to as overlay or clipping, is turned on by setting the OvlEnable parameter to `1'. As long as OvlEnable='0', all pixels within the selected portion of the image are transferred to destination. The masking map is a one bit deep map of the video rectangle. Its location in system memory is defined by a pair of base addresses (one for each field - MaskTopBase, MaskBotBase), and an inter-line stride (MaskStride). The width of the map must be doubleword aligned. Thus, the line size is: int((VidWinWid+31) >> 5) and the number of lines in the map is: 2*VidWinHt, if DispMod==0, or VidWinHt, if DispMod==1. In order to match the 0/1 values of the map to their corresponding pixels in the video rectangle, the map must follow the format given in Table 9. Table 9: Bit, Byte and Doubleword Organization of the Masking Map DWORD Byte Bit Pixel index in line ...1 ...0 7....0 39...32 3 31...24 31...24 2 23...16 23...16 0 1 15... 8 15...8 0 7...0 7...0 9.0 JPEG CODE TRANSFER The data flow direction depends on the JPEG mode of operation. In Motion Video and Still Image Compression, the code is transferred from the CODE bus to the system memory. In Motion Video and Still Image Decompression, the code is transferred from the system memory to the CODE bus. The compressed data in system memory is structured within code buffers. Each code buffer may contain a compressed field or frame (two fields) as specified by a user-configurable bit. The ZR36057 supports four code buffers, defined dynamically in a dedicated table, the Code Buffer Table, in the system memory. Before starting a new JPEG process, the host must load the physical address of the code buffer table into the I_STAT_COM_PTR register of the ZR36057. The actual memory allocated to each code buffer by the operating system may be fragmented. The content of each entry in the code buffer table is a pointer to a secondary Fragment Table. The fragment table contains the pointers to the allocated memory chunks. Figure 9 provides a graphical description of the data structure in the system memory. I_STAT_COM_PTR Code Buffer Table STAT_COM0 STAT_COM1 Fragment Table ADDRESS_0 LENGTH_0 ADDRESS_1 LENGTH_1 F Fragment_0 F Fragment_1 ADDRESS_n-1 LENGTH_n-1 F F=Final Fragment_n-1 STAT_COM2 STAT_COM3 Figure 9. JPEG Code Data Structure In System Memory 9.1 The Code Buffer Table The Code Buffer Table consists of four STAT_COM ("status or command") entries, one for each code buffer. The interpretation of each STAT_COM entry is determined by its l.s. bit, the STAT_BIT. If STAT_BIT='0', the content of the entry is the "com- 20 Enhanced PCI Bus Multimedia Controller mand" information, written by the host, for the next available buffer. Table 10 shows the interpretation for this case. * The host allocates the first four code buffers and writes out the code buffer table and the fragment table. * The host loads the ZR36057's I_STAT_COM_PTR register with the base address of the code buffer table. * After the start of the compression process, the ZR36057 starts filling the fragments of the first code buffer with the compressed data of the first field or frame. * After successfully completing transfer of the compressed data of a field or frame, the ZR36057 writes the status information back to the STAT_COM entry of the current buffer. It sets the STATUS_BIT in the STAT_COM entry, declaring its content as status. It then issues an interrupt, and starts the next field or frame process. * If a new code buffer is unavailable at the beginning of a field or frame process (that is, if the STATUS_BIT of the next buffer entry is `1'), the ZR36057 polls the STAT_COM entry until the buffer is available. * When the host receives the interrupt, it checks the STAT_COM entries in the code buffer table. For each entry whose STAT_BIT='1', the host checks F_CNT to determine whether any fields/frames were dropped. It records the code buffer information, updates the fragment table and STAT_COM entry of the code buffer, and returns it by resetting STAT_BIT to `0'. Several scenarios might cause a field or frame process to be unsuccessful: * The allocated code buffer memory was smaller than the actual field/frame code volume (the ZR36057 fills the final fragment, but the field/frame code transfer is not complete). * A ZR36016 strip memory overflow occurs during the field/ frame compression (might be caused by very large PCI bus latency) After an unsuccessful field/frame process in compression, the ZR36057 does not issue an interrupt, and restarts with the next field or frame. Table 10: STAT_COM entry content, when STAT_BIT=0 Bit 31:2 Content FRAG_TAB_PTR[31:2] Description The address pointer to the fragment table of the next buffer to be used. The 2 l.s. bits of the address must be `0' - that is, the address must be doubleword aligned. Must to be `0`. Must be `0' to indicate that the table entry is a command. 1 0 FRAG_TAB_PTR [1] STAT_BIT If the STAT_BIT=`1`, the content of the entry is the "status" information, written by the ZR36057, of the most recently processed field or frame. Table 11 shows the interpretation for this case. Table 11: STAT_COM entry content, when STAT_BIT=1 Bit 31:24 Content F_CNT[7:0] Description The serial number, modulo 256, of the most recent field or frame. Used in compression only. Reserved, set to `0'. F_LENGTH[21:0] The length of the most recently compressed field or frame in bytes, used in compression only. The length is doubleword aligned, so bits 2..1 are always `0`. `1`, indicating that this table entry is a status written by the ZR36057. 23 22:1 0 STAT_BIT 9.2 Fragment Table The Fragment Table defines the structure of the allocated memory for each code buffer. The table has N entries for N allocated fragments. Each entry holds two doublewords: * first doubleword - the physical address of the fragment (must be doubleword aligned), * second doubleword - the fragment length in doublewords (must be doubleword aligned). The l.s. bit of the second doubleword is the FINAL bit, indicating (when `1') that the current fragment entry defines the last fragment of the buffer. 9.4 JPEG Decompression Modes. The sequence of actions performed by the host software and the ZR36057 is as follows: * The host allocates the first four code buffers and writes out the code buffer table and the fragment table. * The host fills the allocated fragments with the code to be decompressed. * The host loads the ZR36057's I_STAT_COM_PTR register with the base address of the code buffer table. * After the start of the decompression process, the ZR36057 starts reading the code of the first field or frame from the code buffer fragments. * After completing decompression of the field or frame, the ZR36057 sets the STATUS_BIT in the STAT_COM register, 9.3 JPEG Compression Modes The sequence of actions performed by the host software and the ZR36057 is as follows: 21 Enhanced PCI Bus Multimedia Controller declaring that this buffer was already decompressed, issues an interrupt, and starts the next field/frame process. It reads the next STAT_COM entry from the code buffer table. If the buffer is available, that is, the STAT_BIT=`0` indicating it contains the code of a new field/frame, the ZR36057 starts transferring its fragments for decompression. * If a new code buffer is unavailable at the beginning of a field or frame process (that is, if the STATUS_BIT of the next buffer entry is `1'), the ZR36057 repeats decompression of the last available code buffer. * When the host receives the interrupt, it checks the STAT_COM entries in the code buffer table. For each entry whose STAT_BIT='1', the host loads compressed data into a new code buffer and updates its fragment table, then returns the buffer by resetting its STAT_BIT to `0'. Important Note: In Motion Video Decompression mode, if the ZR36057 starts a new fragment when the Code FIFO is exactly full, the Code FIFO can sometimes overflow. There are two possible ways to deal with this problem: 1. Copying the fragmented buffer into a single-fragment buffer before playing it back. Implementing this alternative may cause some performance degradation due to the additional memory-to-memory copying. 2. Configuring the Code FIFO threshold to be low enough. If the Code FIFO threshold is low enough, the Code FIFO will never reach fullness. The maximum length of a single PCI burst is limited, and after the Code FIFO gets above its threshold, the PCI bus is not requested again. The recommended parameters of the ZR36057 for this workaround option are: * The Triton bit (in the Video Display Configuration Register) should be 0. This bit causes the ZR36057's REQ signal to be de-asserted immediately after the bus was granted. Typically (on machines with Triton PCI chip set), this causes the GNT signal to be de-asserted. The ZR36057's burst length is then determined by the Latency Timer parameter. * Master Latency Timer = 48 (in the PCI Configuration Space Register. * JPEGCodTrshold (in the JPEG Code FIFO Threshold Register = 20. 22 Enhanced PCI Bus Multimedia Controller 10.0 RESET There are three means of resetting the ZR36057. One is a hardware reset, which is applied through the PCIRST input, the second is a software reset, which is applied through the SoftReset register bit. The third is the JPEG Process Reset asserted by the P_reset register bit. While in software reset, all registers and state machines in the device are reset to their default values/states, except the SoftReset bit itself, and the PCI Interface (including the PCI configuration space registers). The device continues to respond according to the PCI Specification and can be the target of a PCI transfer targeted at the ASRs (Application Specific Registers) or PCI Configuration Space. While in software reset the device will not initiate any PCI transfers, because all DMA channels are disabled. After the SoftReset bit is deasserted, all registers retain their default values, all DMA channels remain disabled and all ASRs are programmable according to their "normal" modification conditions. Hence, the initialization of the device (loading all registers with the values required for the specific application) must start with setting SoftReset to `1', otherwise new ASR values will not be latched in. 10.1 Hardware Reset The hardware reset signal PCIRST resets the internal state machines in the ZR36057 and loads all registers with their default states. The reset state of the PCI interface pins is as defined by the PCI specifications (2.1). The reset state of the other output/bidirectional signals is as follows. The GPIO[7:0] lines are all inputs after reset. If required for system purposes, they can be pulled high or low through 1 K external resistors to have fixed values on reset. As long as PCIRST is asserted, the following signals are tristated: GDAT[7:0], GADR[2:0], GCS[3:0], GWR, GRD, SDA, SCL. Once the PCIRST input is deasserted, these signals go to their software reset condition (as does the entire device). A hardware reset asserts (clears) the SoftReset bit in the system register. After the hardware reset is over, the ZR36057 will be in software reset condition until the SoftReset bit is deasserted. 10.3 JPEG P_reset The P_reset bit resets all of the JPEG related state machines and controls in the ZR36057. The P_reset bit enables re-configuration of all JPEG parameters with no effect on the other functions of the device. Before starting a new JPEG process, and while loading new JPEG parameters, the P_reset bit must be asserted. 10.2 Software Reset There are two ways in which the ZR36057 can go into the software reset condition: one is right after hardware reset (i.e., upon the low to high transition of PCIRST), the other is by clearing the SoftReset bit. 23 Enhanced PCI Bus Multimedia Controller 11.0 PCI CONFIGURATION SPACE REGISTERS The PCI specification requires that a PCI device include a configuration register space, a set of 256 8-bit configuration registers. The first 64 bytes make up the configuration header, predefined by the specification and the remainder are application specific. These registers allow device relocation, device independent system address map construction and automatic configurations. The configuration registers are accessed by the host software through two consecutive doubleword I/O accesses to physical addresses 0x0CF8 and 0x0CFC, respectively. The host PCI bridge is responsible for translating these accesses to a PCI configuration cycle, including the assertion of the IDSEL input. The ZR36057 then responds to these cycles. This section details the ZR36057's PCI configuration registers. PCI configuration accesses to ZR36057 configuration addresses that are not explicitly described here return zeros (in reads). Table 12: ZR36057 PCI Configuration Space Registers Address Offset 0x00 Bits 31:16 15:0 0x04 31 30 29 28 27 26:25 24 23 22:16 15:10 9 8 7 6 5:3 2 1 0 0x08 31:8 7:0 0x0C 31:24 23:16 15:8 Type R R RC R RC RC RC R R R R R R R R R R RW RW R R R R R RW Device ID. Hardwired to 0x6057. Vendor ID. Hardwired to 0x11DE. Parity Error Detected. This bit is set when a parity error is detected, regardless of the Parity Error Response bit. System Error Signaled. Hardwired to `0'. Master Abort Detected. This bit is set when a master-abort condition has been detected. Target Abort Detected. This bit is set when a target-abort condition has been detected. Target Abort Signaled. When the ZR36057 terminates a transaction as a target (e.g., due to wrong address parity) it sets this bit. DEVSEL Timing. Hardwired to `00' ("fast" timing, i.e., DEVSEL is asserted before rising edge of clock three within a cycle). Data Parity Reported. Hardwired to `0'. Fast Back-to-Back Capability. Hardwired to `0'. Reserved. Returns zeros. Reserved. Returns zeros. Fast Back-to-Back Enable. Hardwired to `0'. System Error Enable. Hardwired to `0'. Wait Cycle (Stepping) Enable. Hardwired to `0'. Parity Error Response. Hardwired to `0'. Unused. Hardwired to `0'. Master Enable. When this bit is set to `1' the ZR36057 can operate as a bus master. Default is `0'. Memory Access Enable. When this bit is set to one the device responds to PCI memory accesses. Default value is `0'. I/O Access Enable. Hardwired to `0'. Class Code. Returns 0x040000 (Multimedia Video Device) Revision ID. Hardwired to 0x01 Unused. Return zeros. Header Type. Returns zeros. Master Latency Timer. The number of PCI clocks that limit ZR36057-initiated bursts in case GNT is deasserted by the bus arbiter during the ZR36057-initiated burst. The 3 LS bits are read-only zeros. The default value is 0x00. Unused. Returns zeros. Memory Base Address. This value determines the base address of the ZR36057 as a memorymapped device. The ZR36057 occupies a range of 4096 bytes out of the memory map: Bits 11:0 are hardwired to `0'. The default value of all other bits is `0'. Hardwired to `0'. Description 7:0 0x10 31:12 11:0 R RW R R 0x14 to 0x3B 24 Enhanced PCI Bus Multimedia Controller Table 12: ZR36057 PCI Configuration Space Registers Address Offset 0x3C Bits 31:24 23:16 15:8 7:0 Type R R R RW Description Max_Lat - Hardwired to 0x10 (i.e., 4 s). This value indicates for the operating system how often the device needs access to the PCI bus. Min_Gnt - Hardwired to 0x2 (i.e., 0.5us). Indicates to the operating system the minimum length of a burst. Interrupt pin. Hardwired to 0x1, indicating that INTA is used. Interrupt Line. These bits indicate the interrupt line that is being used (e.g., IRQ10 ==> 0xA, etc.). Default value is 0xA. 12.0 APPLICATION-SPECIFIC REGISTERS (ASRS) The ZR36057 application-specific registers (ASRs) are memorymapped. Their base address is configured by the host into PCI configuration address 0x10. The ZR36057 claims a contiguous range of 4K bytes of memory. PCI memory-read accesses to addresses (within the 4K range) that are not explicitly described in this section return zeros. The ASRs can be accessed in any byte combination. 9:0 RW vid Address Offset: 0x000 (Continued) Bit 29:20 19:10 Type R RW vid Mod Description Reserved. Returns zero. HStart - Horizontal Start Offset. Number of pixel clocks in a line from the active edge of HSYNC until the first pixel to be sampled. Default value is 0x001. HEnd - Horizontal End Offset. Number of pixel clocks in a line from the active edge of HSYNC until the last pixel to be sampled. Default value is 0x3FF. The column Mod of the following tables defines the conditions under which each parameter of the ASRs is allowed to be modified by the host software. The following abbreviations are used: Abbreviation all res vid cod snap jpg Description This parameter may be modified on the fly, i.e. any time. This parameter is set once after a reset of the ZR36057, no modifications allowed during operation. This parameter may be modified if either VidEn = `0' or SnapShot = `1' and FrameGrab = `0'. This parameter may be modified if CodReadEn = `0'. This parameter may be modified if SnapShot = `1'. This parameter may be modified if P_reset = `0`. 12.2 Video Front End Vertical Configuration Register This 32 bit register contains the vertical configuration parameters of the video source. Address Offset: 0x004 Bit 31 30 Type R RW vid Mod Description Reserved. Returns zero. VSPol - VSYNC Polarity. VStart and VEnd are counted from the active edge of VSYNC. `1' - negative edge of VSYNC. `0' - positive edge of VSYNC (default value). Reserved. Returns zero. vid VStart - Vertical Start Offset. Number of lines from the active edge of VSYNC until the first line to be sampled. Default value is 0x001. VEnd - Vertical End Offset. Number of lines from the active edge of VSYNC until the last line to be sampled. Default value is 0x3FF. Note that after a hard or soft reset VidEn = `0', CodReadEn = `0', and P_reset = `1'. 29:20 19:10 R RW 12.1 Video Front End Horizontal Configuration Register This 32 bit register contains the horizontal configuration parameters of the video source. Address Offset: 0x000 Bit 31 30 Type R RW vid Mod Description Reserved. Returns zero. HSPol - HSYNC Polarity. HStart and HEnd are counted from the active edge of HSYNC. `1' - negative edge of HSYNC. `0' - positive edge of HSYNC (default value). 9:0 RW vid 25 Enhanced PCI Bus Multimedia Controller 12.3 Video Front End, Scaler and Pixel Format Register This register contains the video front end configuration (byte 3), video scaler (bytes 2-1) and pixel formatter (byte 0) parameters Address Offset: 0x008 Bit 31:27 26 Type R RW vid Mod Description Reserved. Returns zero. ExtFI - External Field Indication. `1' - the video source provides an FI signal. `0' - field indication is derived from HSYNC and VSYNC (default value). TopField - Top Field Interpretation. If field indication is derived from the FI input signal (see ExtFI), then this parameter defines which level of FI indicates the top field: `1' - FI high indicates the top field (default value). `0' - FI low indicates the top field. If field indication is derived internally from HSYNC and VSYNC, then this parameter defines which level of HSYNC indicates the top field on the active edge of VSYNC: `1' - HSYNC high indicates the top field (default value). `0' - HSYNC low indicates the top field. VCLKPol - Video Clock Polarity. When set to `0' (default value), the video interface inputs are sampled by the positive edge of VCLKx2 that is qualified by VCLK = `0'. The video interface outputs (other than PXEN) are driven at the negative edge of VCLKx2 which is qualified by VCLK = `1'. When set to `1', the video interface inputs are sampled by the positive edge of VCLKx2 that is qualified by VCLK = `1'. The video interface outputs (other than PXEN) are driven at the negative edge of VCLKx2 which is qualified by VCLK = `0'. HFilter - Horizontal Filter Selection. The following horizontal filters can be selected: 000b - Filter 1 = no luminance, 3-tap chrominance 001b - Filter 2 = 3-tap luminance, 3-tap chrominance 010b - Filter 3 = 4-tap luminance, 4-tap chrominance 011b - Filter 4 = 5-tap luminance, 4-tap chrominance 100b - Filter 5 = 4-tap luminance, 4-tap chrominance 101b - 111b will result in the default filter. Default value 000b. 19:14 RW vid Address Offset: 0x008 (Continued) Bit 20 Type RW Mod vid Description DupFld - Duplicate Field. This parameter has an effect on the vertical decimation of a frame in respect to the video source. The result is less loss of information and less distortion. `1' - indicates top and bottom fields are equal. `0' - indicates an interlaced video source, top and bottom fields are different (default value). HorDcm - Horizontal Decimation Ratio. This parameter defines the number of pixels to be dropped out of every 64 consecutive pixels. 000000b - no horizontal decimation (default value). VerDcm - Vertical Decimation Ratio. This parameter defines the number of lines to be dropped out of every 64 consecutive lines. 000000b - no vertical decimation (default value). Reserved. Returns zero. vid DispMod - Display Mode. `1' - single field. `0' - emulated interlaced video (default value). Reserved. Returns zero. vid YUV2RGB - YUV to RGB Conversion. This parameter defines the pixel output format: 00b - YUV 4:2:2, 01b - RGB 8,8,8, 10b - RGB 5,6,5 (default value), 11b - RGB 5,5,5. ErrDif - Error Diffusion. This parameter has an effect only on RGB 5,6,5 and 5,5,5 output formats. `1' - error diffusion is active `0' - simple truncation of RGB 8,8,8 is executed (default value). Pack24 - 24 Bit Packed Format. This bit is applicable only if YUV2RGB = 01b. `1' - RGB 8,8,8 is packed such that it takes 3 PCI cycles to transfer 4 pixels. `0' - one pixel per PCI cycle is transferred (default value). LittleEndian - Little Endian Format flag. `1' - pixel layout on PCI is little endian (default value). `0' - pixel layout on PCI is gib endian. 25 RW vid 13:8 RW vid 7 6 R RW 5 4:3 R RW 24 RW vid 2 RW vid 1 RW vid 23:21 RW vid 0 RW vid 26 Enhanced PCI Bus Multimedia Controller 12.4 Video Display "Top" Register This register contains the doubleword base address of the top field. Address Offset: 0x00C Bit 31:2 1:0 Type RW R Mod vid Description VidTopBase - Video Top Field Base Address. This is the destination starting address for the top field. Default value is 0xFFFFFFFC. Bits 1..0 are hardwired to 00b. 0 RS snap Address Offset: 0x014 Bit 1 Type RW Mod all Description SnapShot - Frame Grab Mode. If this bit is asserted the ZR36057 goes into frame grab mode. When deasserted continuous display of video is resumed. `1' - frame grab mode. `0' - continuous display mode (default value). FrameGrab - Frame Grabbing Command/ Status. When this bit is asserted by the host and SnapShot is asserted, the ZR36057 will transfer the next two fields (indicated by the VSYNC signal) to memory. At the end of the second field this bit will be cleared internally, indicating that the frame grabbing has been completed and video transfer has been stopped. In case of concurrent accesses to this bit, the result is `0'. `1' - start frame grabbing. `0' - frame grabbing completed (default value). 12.5 Video Display "Bottom" Register This register contains the doubleword base address of the bottom field. Address Offset: 0x010 Bit 31:2 1:0 Type RW R Mod vid Description VidBotBase - Video Bottom Field Base Address. This is the destination starting address for the bottom field. Default value is 0xFFFFFFFC. Bits 1..0 are hardwired to 00b. 12.7 Video Display Configuration Register This register contains the configuration parameters for the video display. Address Offset: 0x018 Bit 31 Type RW Mod all Description VidEn - Video Display Enable. If this bit is cleared by the host, video write DMA transfers are disabled. When enabled, the video DMA controller operates normally. `1' - normal video transfer mode. `0' - video write transfers disabled (default value). MinPix - Minimum Number of doublewords. This parameter defines a threshold value. When the number of doublewords inside the Video FIFO has reached this value a videowrite burst is requested. Default value is 0x0F. Range 0x01 - 0x3C. The l.s. bit of this field (bit 24) is also used to configure the motherboard PCI bridge type, so the actual resolution of MinPix is limited by the Triton bit. When the Triton bit is `1', only odd values of MinPix are supported. When the Triton bit is `0', only even values are supported. Triton - PCI Bridge Controller type. This parameter configures the PCI REQ behavior to match the motherboard PCI bridge characteristics. `0' - Intel `Triton' Bridge Controller. The REQ assertion and de-assertion conditions are modified accordingly. `1' - Other PCI Bridge Controllers. Default value is `1'. This bit is also used as the l.s. bit of MinPix. 12.6 Video Stride, Status and Frame Grab Register This register contains parameters for display addressing (bytes 2-3), status of VFIFO (byte 1) and frame grab control (byte 0). Address Offset: 0x014 Bit 31:18 17:16 Type RW R Mod vid Description DispStride - Display Stride. This register defines the address increment in bytes to be added to the address of the last pixel of a display line, to generate the address of the next consecutive display line. If the address difference between two consecutive display lines is zero (i.e, they are physically consecutive) than DispStride should be set (by the driver software) to zero (if DispMode=1) or to the display line size in bytes (if DispMode=0). Default value is 0xFFFC. Bits 1..0 are hardwired to 00b. Reserved. Returns zero. all VidOvf - Video FIFO Overflow flag. This bit is asserted by the Video FIFO server when an overflow of the Video FIFO occurs. This bit is cleared when the host tries to write `1' to it. In case of concurrent accesses to this bit, it remains `1'. `1' - a VFIFO overflow occurred. `0' - no overflow (default value). Reserved. Returns zero. 30:24 RW vid 15:9 8 R RC 24 RW vid 7:2 R 27 Enhanced PCI Bus Multimedia Controller Address Offset: 0x018 (Continued) Bit 23:22 21:12 Type R RW vid Mod Description Reserved. Returns zero. VidWinHt - Video Window Height. This register defines the number of lines that should be displayed by the ZR36057. If DispMod = 0, VidWinHt is half the number, if DispMod = 1, it is the entire number of display lines. Default value is 0x0F0. Reserved. Returns zero. vid VidWinWid - Video Window Width. This register defines the width of the video window in number of pixels. Default value is 0x3FF. 14:8 7:0 R RW vid 12.10 Overlay Control Register This register contains the parameters controlling overlay (byte 1) and masking map addressing (byte 0). Address Offset: 0x024 Bit 31:16 15 Type R RW vid Mod Description Reserved. Returns zero. OvlEnable - Overlay Enable flag. When enabled the masking information in the video mask is evaluated to allow overlay of other windows or graphics. When disabled the video window is always on top. `1' - overlay enabled, `0' - overlay disabled (default value). Reserved. Returns zero. MaskStride. This register defines the address increment in DWORDs that is needed to get from the end of a mask line to the beginning of the next. If the address difference between two consecutive mask lines in main memory is zero (i.e, they are physically consecutive) then MaskStride should be set (by the driver software) to zero (if DispMode=1) or the mask line size in DWORDs (if DispMode=0). Default value is 0xFF. 11:10 9:0 R RW 12.8 Masking Map "Top" Register This register contains the DWORD base address of the top masking map. Address Offset: 0x01C Bit 31:2 1:0 Type RW R Mod vid Description MaskTopBase - Masking Map Top Base Address. This is the source starting address of the top field for the masking map read transfers. Default value is 0xFFFFFFFC. Bits 1..0 are hardwired to 00b. 12.9 Masking Map "Bottom" Register This register contains the DWORD base address of the bottom masking map. Address Offset: 0x020 Bit 31:2 1:0 Type RW R Mod vid Description MaskBotBase - Masking Map Bottom Base Address. This is the source starting address of the bottom field for the masking map read transfers. Default value is 0xFFFFFFFC. Bits 1..0 are hardwired to 00b. 28 Enhanced PCI Bus Multimedia Controller 12.11 System, PCI and General Purpose Pins Control Register This register contains the software reset bit (byte 3), a PCI control parameter (byte 2) and the General Purpose Pins direction parameter (byte 0). Address Offset: 0x028 Bit 31:25 24 Type R RW all Mod Description Reserved. Returns zero. SoftReset - Software Reset. This bit is asserted by the host to reset the ZR36057. If this bit is set to `0' all resettable registers in the device will be reset to their default value, except: - the SoftReset bit, - the PCI interface. The device continues to respond according to the PCI Specification and can be the target of a PCI transfer targeted at the ASRs or config. space. The transfer (single- or burst-write) asserting this bit will not be terminated abnormally. The device will not initiate any PCI transfers during reset, because all DMA channels are disabled. This register continues to be programmable. During reset, actually, only this bit of the ASRs can be modified by the host (e.g. turning reset off). A power on (hardware) reset also asserts this bit. After the hardware reset is over, a large portion of the ZR36057 (see above) will remain in reset mode until the SoftReset bit is deasserted. After this bit is deasserted, all registers retain their default values, all DMA channels remain disabled and all ASRs are programmable in accordance with their modification condition. `1' - no reset, `0' - reset (default value after power on). Reserved. Returns zero. all WaitState - PCI Wait State Control. This parameter defines the number of wait states inserted by the PCI slave logic. During each PCI transfer cycle to the ZR36057, the device will de-assert TRDY according to this value. Default value 000b. Reserved. Returns zero. res GenPurDir - General Purpose Pins Direction. These eight bits define the direction of the GPIO7..0 pins, respectively. A `1' defines the corresponding pin as an input, a `0' as an output. Default value is 0xFF (all inputs). 3:0 RW res 12.12 General Purpose Pins and GuestBus Control Register (I) This register contains the values for General Purpose outputs (byte 3) and timing parameters for the first four Guests (bytes 1-0). Address Offset: 0x02C Bit 31:24 Type RW Mod all Description GenPurIO - General Purpose Input/Output. The function of this register depends on the setting of GenPurDir. For each pin configured as input (default): - reading this bit will return the current value of the input pin. - writing to an input has no meaning, no change of that bit. For each pin configured as output: - reading this bit will return the value on the corresponding output pin. (If there is no external short circuit, this is the last value written by the host.) - writing will change the output to the value specified. Default value is 0xF0. Reserved. Returns zero. res duration time for guest 3: 00b - Tdur3 = 3 PCI clocks (default value), 01b - Tdur3 = 4 PCI clocks, 10b - Tdur3 = 12 PCI clocks, 11b - Tdur3 = 15 PCI clocks. recovery time for guest 3: 00b - Trec3 = 3 PCI clocks (default value), 01b - Trec3 = 4 PCI clocks, 10b - Trec3 = 12 PCI clocks, 11b - Trec3 = 15 PCI clocks. duration and recovery times for guest 2 (same structure as defined for guest 3 above). duration and recovery times for guest 1 (same structure as defined for guest 3 above). duration and recovery times for guest 0 (same structure as defined for guest 3 above). 23:16 15:14 R RW 13:12 RW res 11:8 RW res 7:4 RW res 23:19 18:16 R RW 12.13 MPEG Code Source Address Register This register contains the DWORD base address for MPEG mode code DMA transfers. Address Offset: 0x030 Bit 31:2 1:0 Type RW R Mod cod Description CodMemBase - MPEG Code Memory Base Address. This is the source starting address for the code-read DMA transfers. Default value is 0xFFFFFFFC. Bits 1..0 are hardwired to 00b. 15:8 7:0 R RW 29 Enhanced PCI Bus Multimedia Controller 12.14 MPEG Code Transfer Control Register This register contains status and control bits and configuration parameters for code DMA transfers. Address Offset: 0x034 Bit 31 30 Type R RC all Mod Description Reserved. Returns zero. CodTime - MPEG Code-Write Timeout flag. This bit is set to `1' by the GuestBus master if a code-write cycle on the GuestBus lasts more than 64 PCI clocks. This might happen when the accessed guest holds GWS low too long. It is cleared (`0') by the host writing a `1'. Priority is given to the GuestBus master in case of concurrent accesses to this bit. `1' - a code-write cycle has timed out. `0' - no timeout occurred (default value). CEmpty - Code FIFO Empty. This bit reflects the status of the internal code buffer. When the buffer is empty this bit shows one, otherwise zero. `1' - Buffer is empty (default value), `0' - Buffer is not empty. cod CFlush - Code FIFO Flush. This bit is used by the host to reset the internal code buffer. When it is asserted remaining code in the buffer is lost. After it is deasserted the buffer is empty and ready to receive data. `1' - flush internal code buffer (default value), `0' - normal operation of buffer. Reserved. Returns zero. cod CodGuestID - Code Guest Identification. These three bits select the guest to be accessed for MPEG code DMA transfers. Default after reset is 000b. Reserved. Returns zero. cod CodGuestReg - MPEG Code Guest Register. Register indication of accessed guest for MPEG code DMA transfers. Within each guest up to eight registers can be addressed. Default after reset is 000b. Unused. Returns zero. cod CodMemSize - MPEG Code Memory Buffer Size. This value determines the size of the contiguous memory buffer allocated by the host for storage of MPEG compressed data: 000b - 8 kbyte, 001b - 16 kbyte, 010b - 32 kbyte, 011b - 64 kbyte (default value), 100b - 128 kbyte, 101b - 256 kbyte. 110b - 111b will result in the default value. Reserved. Returns zero. 0 RW cod 7 RW all Address Offset: 0x034 (Continued) Bit 10:8 Type RW Mod cod Description CodMemStep - MPEG Code Memory Report Step. In MPEG mode, this value determines the amount of code data, in quanta of 8 kbytes, after which the ZR36057 notifies its position (within the buffer) to the host, by requesting an interrupt. For proper operation, the buffer size must be greater than or equal to the report step size: 000b - IRQ every 8 kbytes, 001b - IRQ every 16 kbytes (default value), 010b - IRQ every 32 kbytes, 011b - IRQ every 64 kbytes, 100b - IRQ every 128 kbytes, 101b - IRQ every 256 kbytes. 110b - 111b will result in the default value. CodReadEn - MPEG Code-Read Enable. In MPEG mode, if this bit is cleared by the host, the code-read transfers are stopped. The current code-read pointer retains its value. When this bit is set to `1', the ZR36057 resumes code-read transfers. Default value is `0'. Reserved. Returns zero. cod CodTrshld - MPEG internal code FIFO threshold. In MPEG mode, if the fullness of the FIFO drops below this threshold value (in DWORDs) and CodReadEn is set to `1', a code-read burst is requested. Default value is 0x6. CodAutoEn - MPEG Code-Read Auto Reinitialize Enable. In MPEG mode, if this bit is cleared, every time the code memory pointer reaches the end of the allocated space (i.e. CodMemBase plus CodMemSize) the code-read transfer is stopped. If the bit is set the code memory pointer is reinitialized at the end of the allocated space and code-read transfers run in a cyclic manner. Default value is `0'. 29 R 28 RW 6:4 3:1 R RW 27:23 22:20 R RW 19 18:16 R RW 15 14:12 R RW 11 R 30 Enhanced PCI Bus Multimedia Controller 12.15 MPEG Code Memory Pointer Register This register contains the pointer to the code memory of the host in MPEG mode. Address Offset: 0x038 Bit 31:16 15:0 Type R RW cod Mod Description Unused. Returns zero. CodMemPoint - MPEG Code Memory Pointer. In MPEG mode, this register reflects the current position of the code memory pointer within the range of the allocated host memory. The value represents the number of DWORDs from the base address. Writing to this register by the host can be used for reset or moving the pointer inside the code memory space, only if CodReadEn is deasserted. A value pointing outside the memory size should not be used. Default value is zero. Address Offset: 0x03C (Continued) Bit 27 Type RC Mod all Description JPEGRepIRQ - JPEG Report Interrupt Request. A `1' indicates that a JPEG field/ frame process has ended. In Compression modes, a field compression has ended and its data has been transferred to the allocated code buffer in system memory. In Decompression modes, a field/frame decompression has ended and its corresponding code buffer can be re-loaded by the software. This bit is cleared when the host tries to write `1' to it. In case of concurrent accesses to this bit, it remains `1'. Default value is `0' (no IRQ). Reserved. Returns zero. 26:0 R 12.17 Interrupt Control Register 12.16 Interrupt Status Register This register contains the status of the interrupt sources. Address Offset: 0x03C Bit 31 30 Type R RC all Mod Description Reserved. Returns zero. GIRQ1 - GIRQ1 Input Pin. A `1' indicates that a guest requested an interrupt on the GIRQ1 input pin. This bit is cleared when the host tries to write `1' to it. In case of concurrent accesses to this bit, it remains `1'. Default value is `0' (no IRQ). GIRQ0 - GIRQ0 Input Pin. A `1' indicates that a guest requested an interrupt on the GIRQ0 input pin. This bit is cleared when the host tries to write `1' to it. In case of concurrent accesses to this bit, it remains `1'. Default value is `0' (no IRQ). CodRepIRQ - MPEG Code Report Step Interrupt Request. A `1' indicates that the code memory buffer pointer, in MPEG mode, has passed a report step. This bit is cleared when the host tries to write `1' to it. In case of concurrent accesses to this bit, it remains `1'. Default value is `0' (no IRQ). 30 RW all This register contains the control byte for the interrupt handling. Address Offset: 0x040 Bit 31 Type R Mod Description Reserved for future interrupt source. Returns `0'. GIRQ1En - GIRQ1 Enable. When enabled and IntPinEn is set to `1', each positive edge of the GIRQ1 input will generate an interrupt request on the PCI Bus INTA output pin. When cleared, GIRQ1 continues to reflect the corresponding interrupt pin. `1' - GIRQ1 enabled, `0' - GIRQ1 disabled (default value). GIRQ0En - GIRQ0 Enable. When enabled and IntPinEn is set to `1', each positive edge of the GIRQ0 input will generate an interrupt request on the PCI Bus INTA output pin. When cleared, GIRQ0 continues to reflect the corresponding interrupt pin. `1' - GIRQ0 enabled, `0' - GIRQ0 disabled (default value). CodRepIrqEn - MPEG Mode Code Report Step Interrupt Enable. When enabled and IntPinEn is set to `1', an interrupt request will be generated on the PCI Bus INTA output pin each time the code memory buffer pointer passes a report step. When CodRepIrqEn is cleared, CodRepIrq continues to reflect the internal report step interrupt request. `1' - interrupt request enabled, `0' - disabled (default value). 29 RC all 29 RW all 28 RC all 28 RW all 31 Enhanced PCI Bus Multimedia Controller Address Offset: 0x040 (Continued) Bit 27 Type RW Mod all Description JPEGRepIRQEn - JPEG Report Interrupt Request Enable. When enabled and IntPinEn is set to `1', an interrupt request will be generated on the PCI Bus INTA output pin after the end of each JPEG field/frame process. When JPEGRepIRQEn is cleared, JPEGRepIRQ continues to reflect the JPEG process status. `1' - interrupt request enabled, `0' - disabled (default value). Reserved. Returns zero. all 12.19 PostOffice Register This register contains the status (byte 3), control (byte 2) and data (byte 0) parameters for PostOffice transfers. Address Offset: 0x200 - 0x2FF Bit 31:26 25 Type R R all Mod Description Reserved. Returns zero. POPen - PostOffice Request Pending flag. This bit is set internally to `1' when the host writes to the PostOffice data byte. It is cleared when a PostOffice cycle is completed or a PostOffice time-out occurred. In case of concurrent accesses to this bit, the result is `0'. `1' - PostOffice request is pending. `0' - PostOffice request is not pending (default value). POTime - PostOffice Time-out flag. This bit is set to `1' by the GuestBus master if a PostOffice cycle on the GuestBus lasts more than 64 PCI clocks. This might happen when the accessed guest holds GWS low for too long. It is cleared (`0') by the host writing a `1'. In case of concurrent accesses to this bit, it remains `1'. `1' - PostOffice cycle has timed out. `0' - no time-out occurred (default value). PODir - PostOffice Direction flag. This bit defines the direction of the PostOffice operation: `0' - Read (host reads guest). `1' - Write (host writes to guest). Default after reset is `1'. POGuestID - PostOffice Guest Identification. These three bits select the guest to be accessed. They determine which of the GCS pins will be asserted in the requested PostOffice cycle. Up to eight guests can be identified. Default after reset is 000b. Reserved. Returns zero. all POGuestReg - PostOffice Guest Register. Register indication of accessed guest. Within each guest up to eight registers can be addressed. The POGuestReg bits determine the register address that will be presented on the GADR2:0 lines in the requested PostOffice cycle. Default after reset is 000b. Reserved. Returns zero. all POData - PostOffice Data. An eight-bit register containing the data being transferred during PostOffice reads and writes. Default after reset is 00000000b. 26:25 24 R RW IntPinEn - INTA Pin Enable. When cleared, none of the events that may cause an interrupt request on the PCI Bus INTA pin is enabled. Nevertheless the interrupt status register continues to reflect all interrupt input pins and internal interrupt requests. `1' - every interrupt request is passed onto the PCI Bus, `0' - INTA disabled (default value). Reserved. Returns zero. 24 RC all 23:0 R 12.18 I2C-Bus Register This register contains the control bits of the I2C Bus. Address Offset: 0x044 Bit 31:2 1 Type R RW all Mod Description Unused. Returns zero. SDA - I2C SDA Line. When the host writes `0' to this bit, the SDA output signal goes low. When the host writes `1', SDA goes into tristate. When the host reads this bit it reflects the current level on the SDA pin. Default value is `1'. SCL - I2C SCL Line. When the host writes `0' to this bit, the SCL output signal goes low. When the host writes `1', SCL goes into tristate. When the host reads this bit it reflects the current level on the SCL pin. Default value is `1'. 23 RW all 22: 20 RW all 0 RW all 19 18:16 R RW 15:8 7:0 R R, W 32 Enhanced PCI Bus Multimedia Controller 12.20 JPEG Mode and Control This register contains the JPEG Mode configuration and optional control bits. Address Offset: 0x100 Bit 31 Type RW Mod all Description JPG- JPEG/MPEG mode selection. This bit selects between the two code DMA controller modes. `1' - JPEG Mode. `0' - MPEG Mode. Default value is `0` JPGMode - JPEG Sub-Modes Selection. These two bits configure the JPEG submode. 11b - Motion Video Compression. 10b - Motion Video Decompression. 01b - Still Image Compression. 00b - Still Image Decompression. Default value is 11b Reserved. Returns zero. jpg RTBSY_FB - RTBSY Feed-Back. This control bit enables the ZR36057 to de-assert dynamically (during a process) the PXEN signal if RTBSY is detected in the active area of the field. `1' - Enable PXEN de-assertion if RTBSY is detected. `0' - Disable PXEN de-assertion. Default value is `0' Go_en - The enable bit of the ZR36050 GO command cycle. The bit, when `1', enables the GuestBus Master to perform a JPEG GO cycle. During the JPEG GO cycle the ZR36057 assumes that the correct address (0x00h) is pre-latched in an external address register. It is the host's responsibility to perform the write operation to load the address. The host must de-assert Go_en whenever it accesses the ZR36050 (using PostOffice) in a middle of a JPEG process, or changes the address latched in the external register. The host must also de-assert Go_en before PostOffice pseudo write-through burst cycles. In this case, the host also has to wait at least 0.5 microseconds before initiating the burst (to allow the JPEG GO cycle to complete, if one was started). Default value is `0' (Go not enabled). jpg SyncMstr - Sync Signals Master. This bit configures the ZR36057 as a sync master. This configuration is allowed in all JPEG modes except Motion Video Compression `1' - The ZR36057 is the sync signal master. `0' - The sync signals are driven from an external video source. Default value is `0' Address Offset: 0x100 (Continued) Bit 3 Type RW Mod jpg Description Fld_per_buff - Number of Fields Per Code Buffer. This bit reflects the system memory code buffer structure in JPEG Compression and Decompression modes. `1' - The code buffer contains one code field. `0' - The code buffer contains two consecutive code fields, one code frame. Default value is `0` VFIFO_FB - VFIFO Feed-Back. This control bit enables the ZR36057 to de-assert dynamically (during a process) the PXEN signal according to the status of the Video FIFO. `1' - Enable PXEN de-assertion if the pixel buffer is close to overflow. `0' - Disable PXEN de-assertion if the pixel buffer is close to overflow. Default value is `0' CFIFO_FB - CFIFO Feed-Back. This control bit enables the ZR36057 to de-assert dynamically (during a process) the PXEN signal according to the status of the Code FIFO. `1' - Enable PXEN de-assertion if the code buffer is close to overflow/underflow. `0' - Disable PXEN de-assertion if the code buffer is close to overflow/underflow. Default value is `0' Still_LitEndian - Still image pixel Little Endian format selector. This control bit defines the pixel format in Still Image Compression and Decompression. `1' - The pixel format is Little Endian. `0' - The pixel format is Gib Endian. Default value is `1'. 2 RW jpg 30 : 29 RW jpg 1 RW jpg 28 : 7 6 R RW 0 RW jpg 5 RW 12.21 JPEG Process Control This register contains the JPEG process control. Address Offset: 0x104 Bit 31: 8 7 Type R RW all Mod Description Reserved. Returns zero. P_reset - Process Reset. This bit is asserted by the host in order to reset the ZR36057 JPEG-related state machines. The bit must be asserted at the beginning of a JPEG process. While it is asserted, all of the JPEG process parameters may be configured by the host. `1' - No reset. `0' - Reset. Default value is `1'. Reserved, Returns zero. CodTrnsEn - JPEG Code Transfer Enable. This bit enables the code transfer between the internal code buffer and the system memory in all of the JPEG modes. `1' - Code transfer is enabled. `0' - code transfer is disabled. Default value is `0'. 4 RW 6 5 R RW 33 Enhanced PCI Bus Multimedia Controller Address Offset: 0x104 Bit 4:1 0 Type R RW all Mod Description Reserved, Returns zero. Active - This command bit is asserted by the host in order to initiate a JPEG process. `1' - Active is asserted. `0' - Active is deasserted. Default value is `0'. 12.25 Field Vertical Active Portion This register contains the vertical parameters of the active portion of the processed field. Address Offset: 0x114 Bit 31 : 16 Type RW Mod jpg Description NAY - The first line in a field to be processed. Counted from the active edge of VSYNC. Default value is 0x000A. PAY - The number of lines to be processed in a field. Default Value is 0x00F0 (240, for NTSC) 12.22 Vertical Sync Parameters This register contains the VSYNC parameters to be generated by the ZR36057 as a sync master. Address Offset: 0x108 Bit 31: 24 23: 16 Type RW RW jpg Mod Description Reserved. Returns zero. VsyncSize - VSYNC signal length. The VSYNC length is measured in lines. Default value is 0x06. FrmTot - Frame total size. The total number of lines per frame. This parameter must be an odd number. Default Value is 0x020D (525, for NTSC) 15 : 0 RW jpg 12.26 Field Process Parameters This register contains the general parameters of the field process. Address Offset: 0x118 Bit 31 : 1 0 Type R RW jpg Mod Description Reserved. Returns zero. Odd_Even - First field type. The type of the first field to be processed. Odd type is defined as the field in which the active edge of VSYNC is asserted during the active portion of the horizontal line. Even type is defined as the field in which the active edge of VSYNC is asserted during the active portion of HSYNC. `1' - The first field is Odd. `0' - The first field is Even. Default value is `1`. 15 : 0 RW jpg 12.23 Horizontal Sync Parameters This register contains the HSYNC parameters to be generated by the ZR36057 as a sync master. Address Offset: 0x10C Bit 31 : 16 Type RW Mod jpg Description HsyncStart - HSYNC signal Start point. The point in the line (measured in number of VCLKs) at which HSYNC should be asserted. Default value is 0x0280 (640, for square pixel NTSC). LineTot - Line total size. The total number VCLKs in a line. Default Value is 0x030C (780, for square pixel NTSC) 12.27 JPEG Code Base Address This register specifies the base address of the code buffer table. Address Offset: 0x11C Bit 31 : 0 Type RW Mod jpg Description I_STAT_COM_PTR - The memory address of the code buffer table. Default value 0xFFFFFFFC. 15 : 0 RW jpg 12.24 Field Horizontal Active Portion This register contains the horizontal parameters of the active portion of the processed field. Address Offset: 0x110 12.28 JPEG Code FIFO Threshold This register specifies Code FIFO threshold in JPEG mode. Address Offset: 0x120 Bit Type R RW jpg Mod Description Reserved, Returns zero. JPEGCodTrshld - JPEG code FIFO Threshold. In Compression, if the fullness level of the Code FIFO (in doublewords) goes above this threshold the PCI bus is requested. In Decompression, if the fullness level of the Code FIFO (in doublewords) goes under this threshold the PCI bus is requested. Default value is 0x50h Bit 31 : 16 Type RW Mod jpg Description NAX - The first pixel in a line to be processed. Counted from the active edge of HSYNC. Default value is 0x0000. PAX - The number of pixels to be processed in a line. Default Value is 0x0280 (640, for square pixel NTSC) 31 : 8 7:0 15 : 0 RW jpg 34 Enhanced PCI Bus Multimedia Controller 12.29 JPEG Codec Guest ID This register contains the ZR36050 Guest ID for the JPEG GO command cycle. Address Offset: 0x124 Bit 31 :7 6:4 Type R RW jpg Mod Description Reserved, Returns zero. JPEGuestID - JPEG Codec Guest ID. These three bits define the guest port to which the ZR36050 is connected, in order to perform the JPEG GO command cycle. Default value is 100b Reserved, Returns zero. jpg JPEGuestReg - JPEG Codec Register. These three bits define the ZR36050 internal register address for the JPEG GO command. Default value is 000b 12.31 "Still Transfer" Register This register is used for data and control in Still Image Compression or Decompression. Address Offset: 0x140 Bit 31/7 Type R Mod all Description Still_Bsy - Still Transfer Busy indication bit. The bit indicates to the host whether the "Still Transfer" register is available to write the next pixel in Still Image Compression mode. When this bit is `0', the register is available. The bit location depends on the Still_LitEndian configuration bit in the JPEG Mode and Control register. If Little Endian format was selected then the bit location is 31. If Gib Endian format was selected then the bit location is 7. When Still Image Compression mode is selected (and after P_reset was de-asserted), the bit is `0'. After the host writes a pixel, the bit is set to `1'. The bit remains `1' until the pixel is synchronized to the video clock and going to be driven out from the ZR36057 video port. Then when the register is available again, the bit is reset to `0'. When Still Image Decompression mode is selected (and after P_reset was de-asserted), the bit is `1'. After the ZR36057 fetches a new pixel, and the pixel is ready for the host to read it, the bit is reset to `0'. It is set to `1' again after the pixel was read. `1' - The register is not available. `0' - The register is available. Default value is `0'. Still Transfer Pixel register. The byte order (RGB or BGR) is defined by the Still_LitEndian configuration bit in the JPEG Mode and Control register. If Little Endian format was selected, the byte order is: R7..0 on bits 23..16. G7..0 on bits 15..8. B7..0 on bits7..0. If Gib Endian format was selected, the byte order is: R7..0 on bits 15..8. G7..0 on bits 23..16. B7..0 on bits 31..24. 3 2:0 R RW 12.30 GuestBus Control Register (II) This register contains the timing parameters of an additional 4 guests (the first 4 guests' parameters are defined in 12.12 "General Purpose Pins and GuestBus Control Register (I)"). Address Offset: 0x12C Bit 31 : 16 15 : 14 Type R RW res Mod Description Reserved, Returns zero. Duration time for guest 7: 00b - Tdur7 = 3 PCI clocks (default value), 01b - Tdur7 = 4 PCI clocks, 10b - Tdur7 = 12 PCI clocks, 11b - Tdur7 = 15 PCI clocks. Recovery time for guest 7: 00b - Trec7 = 3 PCI clocks (default value), 01b - Trec7 = 4 PCI clocks, 10b - Trec7 = 12 PCI clocks, 11b - Trec7 = 15 PCI clocks. Duration and recovery time of guest 6 (same structure as defined for guest 7 above) Duration and recovery time of guest 5 (same structure as defined for guest 7 above) Duration and recovery time of guest 4 (same structure as defined for guest 7 above) 31 : 0 RW all 13 :12 RW res 11 : 8 7:4 3:0 RW RW RW res res res 35 Enhanced PCI Bus Multimedia Controller 13.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Storage Temperature .........................................65C to +150C Supply Voltage (VDD) ........................................-0.5 V to +6.0 V DC Output Voltage ........................................ 0.5 V to VDD + 0.5 DC Input Voltage.......................................... -0.5 V to VDD + 0.5 DC Output Current .....................................-100 mA to +100 mA DC Input Current ........................................-100 mA to +100 mA Max Power Dissipation .................................... 1.6W @ 33 MHz NOTE: Stresses above these values may cause permanent device failure. Functionality at or above those limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGE Temperature...........................................................0C to +70C Supply Voltage.................................................. 4.75 V to 5.25 V DC CHARACTERISTICS Table 13: Digital Inputs Symbol V IL VIH VIIL VIIH ILI CIN Input low voltage Input high voltage Input low voltage (SDA, SCL) Input high voltage (SDA, SCL) input leakage current input capacitance 0.7 x VDD 2.0 0.3 x V DD Parameter Min Max 0.8 Unit V V V V A pF Test Conditions 10 [1] 8 1. Input Pullup Leakage Current for SDA is -200 A. Table 14: Digital Outputs Symbol V OL VOH ILO COUT Output low voltage Output high voltage Output leakage current Output capacitance 3.8 Parameter Min Max 0.4 Unit V V A pF Test Conditions 10 8 Table 15: PCI Bus Symbol V IL VIH VOL VOH ILIH CPCICLK Input low voltage Input high voltage Output low voltage Output high voltage Input leakage current PCICLK input capacitance 5 2.4 2.0 0.55 Parameter Min Max 0.8 Unit V V V V A pF Test Conditions 70 12 V IN = 2.7/0.5 V 36 Enhanced PCI Bus Multimedia Controller 14.0 AC TIMING SPECIFICATIONS 14.1 PCI Bus Timing Table 16: PCI Bus Timing Symbol tPCI tPH tPL tA3 tA4 tA5 tA6 tA7 tA8 tA9 tA10 tA11 PCICLK period PCICLK high PCICLK low PCICLK slew rate PCICLK to signal valid delay - bussed signals PCICLK to signal valid delay - point-to-point Float to active delay Active to float delay Input setup time to PCICLK - bussed signals Input setup time to PCICLK - point-to-point Input hold time from PCICLK Unoaded output rise/fall time 7 10 0 1 5 Parameter Min 30 12 12 1 2 2 2 4 11 12 11 28 Max Unit ns ns ns V/ns ns ns ns ns ns ns ns V/ns Between 0.4 V and 2.4 V tPCI tPH PCICLK tA4 tA5 Output Delay tPL tA3 tA6 3-State Output tA8 tA9 Input tA10 tA7 tA11 Figure 10. Video Bus Timing 37 Enhanced PCI Bus Multimedia Controller 14.2 Video Bus Timing Table 17: Video Bus Timing Symbol tV2P tV2T tVT tVIS tVIH tVCLKH VCLKx2 period VCLKx2 rise/fall transition VCLK rise/fall transition Video bus input setup Video bus input hold VCLK hold 11 0 -2 Parameter Min 31 Max 45 5 5 Unit ns ns ns ns ns ns 40% to 60% duty cycle tV2P VCLKx2 tVCLKH tV2T tV2T tVIS VCLK tVIS INPUTS tVIH Figure 11. Video Bus Timing Table 18: Video Bus Outputs Symbol tVBO tVBH tVPO tVPH Video bus output delay Video bus output hold (all signals except PXEN) PXEN output delay PXEN output hold 2 Parameter Min 1 1 17 Max 16 Unit ns ns ns ns Typical output Load 50pf VCLK VCLKx2 tVBO VIDEO OUTPUT tVBH tVPO PXEN tVPH Figure 12. Video Bus Timing - Control and Data Output Signals 38 Enhanced PCI Bus Multimedia Controller 14.3 GuestBus Timing Table 19: GuestBus Interface Timing Symbol tCARW tRWCA tRWDUR tRWREC tPD tGDH tGRS tGRH tGIRQ tGWS tGWL tGWH Parameter GCSn / GADR2..0 setup GCSn / GADR2..0 hold GWR / GRD low GWR / GRD high Propagation delay. PCICLK to output signal Write data hold. GWR / GRD to data float Read data setup Read data hold GIRQ1..0 high / low Wait state setup. GWS to GWR/GRD Wait state low [1] Wait state hold. GWS to GWR/GRD 11 0 2 * tPCI (tDUR -1) * tPCP -tPD tGRS tPCI tPCP + tPD + tGRS Min 16 16 90 90 1 16 16 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns Determined by parameter T dur and signal GWS Determined by parameter T rec Typical output load 70 pF Typical output load 70 pF 1. For each period of tPCI the duration of the transfer will be extended for one PCI clock period. 1 PCICLK 2 3 4 5 6 7 8 9 10 11 12 13 tPD GCSn GADR[2:0] tCAR GWR tRWDUR tRWC tCAR tRWREC GRD tRWDU tRWC GWS tGDH GDAT[7:0] Data Valid from ZR36057 tGRS tGRH Data Valid from Guest n Wait-State Timing tRWDUR tDUR GRD/GWR tGWS tGWL GWS tGWH Figure 13. GuestBus Timing 39 Enhanced PCI Bus Multimedia Controller 14.3.1 Codec Bus Interface Timing Table 20: Symbol tCCS tCCH tCPD tCHD tCIS tCIH tCBO tCBH tCES tCEH CCS setup CCS hold Code output propagation delay Code output hold delay Code input setup Code input hold CBUSY output propagation delay CBUSY output hold delay CEND setup CEND hold Parameter Min 10 0 3 1 9 0 2 2 9 1 16 9 Max Unit ns ns ns ns ns ns ns ns ns ns Typical load 15pF Typical load 15pF VCLKx2 tCCS CCS tCC tCCS tCPD CODE[7:0] tCHD tCIS tCIH Data Valid from Codec tCBO CBUSY tCBH tCES CEND tCEH Figure 14. Codec Interface Timing 40 Enhanced PCI Bus Multimedia Controller 15.0 MECHANICAL DATA 15.1 Pinout Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin Name VSS VDD VSS IDSEL AD23 VSS AD22 AD21 VSS AD20 AD19 VDD VSS AD18 AD17 VSS AD16 VDD C/BE2 VSS FRAME IRDY VDD VSS TRDY VSS Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin Name DEVSEL VSS STOP PAR VSS C/BE1 VDD AD15 VSS AD14 VSS AD13 AD12 VSS AD11 C/BE0 VSS VDD AD10 AD9 VSS AD8 AD7 VSS VDD VDD Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Pin Name VSS VDD AD6 AD5 VSS AD4 AD3 VSS AD2 AD1 VSS AD0 VDD SCL SDA VSS VDD GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VSS Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Pin Name GIRQ0 GIRQ1 VDD GCS0 GCS1 GCS2 GCS3 GCS4 VSS VSS VDD GCS5 GCS6 GCS7 VSS VDD GADR0 GADR1 VDD GADR2 GDAT0 GDAT1 GDAT2 VSS VSS VDD Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 Pin Name VSS VDD GDAT3 VSS GDAT4 GDAT5 VSS GDAT6 GDAT7 VDD GWS GRDY GWR GRD VDD VSS CEND CODE0 CODE1 CODE2 CODE3 VSS VCLKx2 VSS CODE4 CODE5 Pin No. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Pin Name CODE6 VDD CODE7 CBUSY VSS CCS VSS VCLK VDD START RTBSY PXEN FI VDD VSYNC HSYNC VSS B0 B1 B2 B3 B4 VSS VDD VDD VSS Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 Pin Name B5 B6 B7 VDD UV0 VSS UV1 UV2 VSS UV3 UV4 UV5 UV6 UV7 VSS VDD Y0 Y1 Y2 Y3 Y4 Y5 Y6 VSS Y7 ENID Pin No. 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Name TEST INTA VDD PCIRST PCICLK GNT VSS REQ AD31 VDD VSS AD30 AD29 VSS AD28 AD27 VSS AD26 AD25 VSS AD24 C/BE3 VSS VDD VDD VSS 41 Enhanced PCI Bus Multimedia Controller VSS VDD VDD VSS C/BE3 AD24 VSS AD25 AD26 VSS AD27 AD28 VSS AD29 AD30 VSS VDD AD31 REQ VSS GNT PCICLK PCIRST VDD INTA TEST ENID Y7 VSS 208 Y6 Y5 Y4 Y3 Y2 Y1 Y0 VDD VSS UV7 UV6 UV5 UV4 UV3 VSS UV2 UV1 VSS UV0 VDD B7 B6 B5 1 VSS VDD VSS IDSEL AD23 VSS AD22 AD21 VSS AD20 AD19 VDD VSS AD18 AD17 VSS AD16 VDD C/BE2 VSS FRAME IRDY VDD VSS TRDY VSS DEVSEL VSS STOP PAR VSS C/BE1 VDD AD15 VSS AD14 VSS AD13 AD12 VSS AD11 C/BE0 VSS VDD AD10 AD9 VSS AD8 AD7 VSS VDD VDD 52 104 53 157 156 ZR36057 (TOP VIEW) VSS VDD VDD VSS B4 B3 B2 B1 B0 VSS HSYNC VSYNC VDD FI PXEN RTBSY START VDD VCLK VSS CCS VSS CBUSY CODE7 VDD CODE6 CODE5 CODE4 VSS VCLKx2 VSS CODE3 CODE2 CODE1 CODE0 CEND VSS VDD GRD GWR GRDY GWS VDD GDAT7 GDAT6 VSS GDAT5 GDAT4 VSS GDAT3 VDD VSS 105 VSS VDD AD6 AD5 VSS AD4 AD3 VSS AD2 AD1 VSS AD0 VDD SCL SDA VSS VDD GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VSS GIRQ0 GIRQ1 VDD GCS0 GCS1 GCS2 GCS3 GCS4 VSS VSS VDD GCS5 GCS6 GCS7 VSS VDD GADR0 GADR1 VDD GADR2 GDAT0 GDAT1 GDAT2 VSS VSS VDD 42 Enhanced PCI Bus Multimedia Controller 15.2 Dimensions 31.1 0.4 SQ. 28.0 0.2 SQ. 25.5 REF. 157 104 ZR36057 (Top View) Pin 1 Index 208 1 52 53 0.50 Nom. 0.23 0.08 3.4 0.4 1.60 REF. 0~7 SEATING PLANE 0.30 0.05 Dimensions in millimeters 0.8 0.2 43 Enhanced PCI Bus Multimedia Controller Appendix A: ZR36100 - ZR36057 Interface Figure 15 describes a recommended interconnection between the ZR36057 and the ZR36100/ZR36110 host bus. Other Guests ZR36100/110 DREQ DACK BUSCS BUSWR BUSRD BUSADD[1:0] BUSDAT[7:0] READY IDLE RESET VSYNC (Optional) ZR36100 Initialization The initialization consists of loading the ZR36100 microcodes and parameters. This is done using the PostOffice mechanism. The host interface of the ZR36100 must be set to 8 bit, Intel format, I/O only. The BSLN parameter should be set to 2 or 4, for efficient operation. On-Line Commands and Status On-line command writes and status reads are also done using the PostOffice mechanism. Bitstream Transfer Some preparations must be done prior to triggering the ZR36100 with a go command. The host must allocate a contiguous code buffer in the system memory. Bitstream retrieved from the MPEG source is stored in this buffer. The ZR36057 reads data from this buffer in a DMA fashion and transfers it, through the CFIFO, to the MPEG decoder. There are several possible sizes of the memory buffer. The host must inform the ZR36057 of the buffer address, size and "report step". After the code buffer in memory is allocated, reported to the ZR36057, and filled up for the first time, a ZR36100 go command can be issued. Immediately after this, the DMA code-read cycles must be enabled by setting the DMA Code-Read Enable bit to `1'. The ZR36057 then starts fetching data from the main memory buffer using cyclic addressing. Whenever it passes a "report step" it initializes an interrupt request. Within the interrupt service routine the host should check the current position of the ZR36057 Code Memory Buffer Pointer, and decide weather it should refresh an old portion of the buffer with new data from the MPEG source. Once the coded data arrives at the CFIFO, the GBM unit starts writing it over the GuestBus to the ZR36100. VDD ZR36057 GCSn GWR GRD GADR[2:0] GDAT[7:0] GRDY GIRQ0 GPIO0 GIRQ1 (Optional) Figure 15. ZR36057 - ZR36100/110 Basic Interconnection ZR36100 Reset Any of the software controlled GPI/O pins (configured as output) of the ZR36057 may be used as a RESET input of the decoder. The software then directly manipulates the RESET signal through the corresponding register bit. Since the default configuration of the GPIO pins after reset is input, a pull down resistor should be applied to the ZR36100 RESET input. Mapping the ZR36100 on the ZR36057's GuestBus The driver software must map the ZR36100 on the GuestBus: the ZR36100's guest ID number (0,1,2, or 3) must be configured as a code-write target. The proper timing parameters (tdur = 3, to ensure 82ns, trec = 4, to ensure 100ns) of the ZR36100 must be loaded to the GuestBus control register (address 0x030). The ZR36100 occupies only four 8-bit registers out of the eight registers dedicated to each guest. 44 Enhanced PCI Bus Multimedia Controller Appendix B: MD207/MD208 - ZR36057 Interface This appendix suggests the basic interconnection between the ZR36057 and the MD207/208 video encoder. Naturally, when these two devices are connected together there must be a third device, mastering the YUV bus. Figure describes a basic interconnection between the ZR36057 and the MD207/208, with an arbitrary YUV source. This minimum example does not use the graphics overlay capability of the MD207/208 Other Guests MD207A/208 CS RS RD WR D[7:0] RESET Test/Fldintr VCLK HSYNC VSYNC BLANK YD[7:0] CD[7:0] (Optional) (Optional) (Optional) Mapping the MD207/208 on the ZR36057's GuestBus The software driver must map the MD207/208 on the GuestBus. The proper timing parameters (tdur = 12, trec = 15) of the MD207/ 208 must be loaded to the GuestBus control register. Reading/writing one byte from/to the MD207/208 requires two GuestBus cycles: in the first cycle the address (index) of the internal MD207/208 register is written, in the second one the data byte is read/written. The RS (register select) input of the MD207/208 is used to distinguish between the two types of cycles. Connecting this pin to the ZR36057's GADR0 virtually creates two MD207/208 registers at the level of the GuestBus: when GADR0 is low (even registers), the MD207/208 expects address to be transferred on its D7:0 bus, when GADR0 is high (odd registers) data is output or input on these lines. Another way is to connect GADR2 to RS. VDD ZR36057 GCSn GADR[0] GRD GWR GDAT[7:0] GPI/On GPI/On VCLKx2 VCLK HSYNC VSYNC Sync Polarity Y[7:0] U/V[7:0] YUV 4:2:2 Source Figure 16. ZR36057 - MD207/208 Basic Interconnection MD207/208 Reset Software controlled usage of the RESET input of the MD207/208 is optional. Generally, it is more efficient to connect it to the power-up reset of the circuit, and control the device through the software reset register bit of the MD207/208. If a hardware reset is needed in the design, any of the software controlled GPI/O pins (configured as output) of the ZR36057 may be used as a RESET signal. The software then directly manipulates the RESET signal through the corresponding register bit of the ZR36057. Since the default configuration of the GPI/O pins after reset is input, a pull down resistor should be applied to the MD207/208 RESET input. Since, unlike the ZR36057, the sync polarity of the MD207/208 is not programmable, then, depending on the YUV 4:2:2 source, it might be necessary to invert the HSYNC and VSYNC of the MD207/208. Vertical Interpolation with the MD208 Pin 8 is the only one that is different between the MD207A and the MD208. While in the MD207A it is a test pin, normally connected to ground, the MD208 uses this input to switch its internal vertical interpolation mechanism on and off. When this mechanism is on, one field out of every pair is vertically interpolated and the interpolated lines are the ones sent out. Since this operation is not always desired (e.g., in high resolution still pictures of VideoCD 2.0) it must be controlled by the software. The natural way to obtain this control is using one of the GPI/Os. It is better to pull this pin down in order for the same layout to support both the MD207A and the MD208. 45 Enhanced PCI Bus Multimedia Controller Appendix C: Fitting the Input Size to the Required Display Window The ZR36057 can crop the input video and scale it down to match any display size required by different applications, as long as the required size is not larger than the original input. This appendix provides some programming guidelines for proper setting of the ZR36057 parameters involved in this process. For better understanding, a typical example is detailed along with the general explanations. It is assumed that the driver software "knows" the following basic parameters about the incoming video: Wt Wa Ht Ha Total width of the input field (i.e., in CCIR NTSC Wt = 858). Active width of the input field (i.e., in CCIR NTSC Wa = 720). Total height of the input frame (i.e., in CCIR NTSC Ht = 525). Active height of the input frame (i.e., in CCIR NTSC Ht = 480). be filled with video pixels. This is referred to as the destination rectangle: VidWinWid VidWinHt Width of the video rectangle. If DispMode=1 (single field display) this is the height of the video rectangle. If DispMode=0 (emulation of interlaced video) this is half of the height of the video rectangle (i.e., the height of one destination field). Note that if DispMode=0 the vertical size of the video rectangle must be an even number. This limitation might conflict with applications that will require a video window of a specific, odd vertical size. Such conflicts will be resolved by the driver software, which in this case will build a rectangle one line shorter than required, and then fill-in the missing line (a-priori) with a background color. It is assumed that Ha is an even number. It is also assumed that from knowing the video input format, the driver knows how to set the following ZR36057 parameters, such that the entire active portion of the video input would have been sampled: HSPol VSPol HStart' HEnd' The polarity of HSYNC, as defined in the ZR36057 data sheet. The polarity of VSYNC, as defined in the ZR36057 data sheet. The number of pixels, from the active edge of HSYNC, after which the ZR36057 starts to sample the input. The number of pixels, from the active edge of HSYNC, after which the ZR36057 stops sampling the input. Obviously, in many cases the size of the video rectangle to be displayed is different (smaller) than the size of the active video input sampled by the ZR36057. In the example: VidWinWid = 597, VidWinHt = 199. (Assuming DispMod = 0, this means that the target "video window" in the example is 597x398). In such cases, out of the parameters above, the driver software must determine the following ZR36057 parameters, such that the quality of the displayed video is optimal in the sense that the decimation factors will be as small as possible and the portions of the input that are "cut out" (cropped) will also be as small as possible. hcrop1 The number of pixels, that will be dropped from the beginning of the active line. hcrop1 is not really a ZR36057 parameter, but it is useful to obtain HStart: HStart = HStart' + hcrop1. hcrop2 The number of pixels, that will be dropped from the end of the active line. hcrop2 is not really a ZR36057 parameter, but it is useful to obtain HEnd: HEnd = HEnd' - hcrop2. vcrop1 The number of lines, that will be dropped from the beginning of the active field. vcrop1 is not really a ZR36057 parameter, but it is useful to obtain VStart: VStart = VStart' + vcrop1. vcrop2 The number of lines, that will be dropped from the end of the active field. vcrop2 is not really a ZR36057 parameter, but it is useful to obtain VEnd: VEnd = VEnd' - vcrop2. The following equation connects HStart', HEnd', and Wa: Wa = HEnd' - HStart' + 1 In the example, Hend' = 841, HStart' = 122. VStart' VEnd' The number of lines, from the active edge of VSYNC, after which the ZR36057 starts to sample the input. The number of lines, from the active edge of VSYNC, after which the ZR36057 stops sampling the input. The following equation connects VStart', VEnd', and Ha: Ha/2 = VEnd' - VStart' + 1 In the example, Vend' = 249, VStart' = 10. The driver receives from the application software the parameters that define the size of the rectangle, on the monitor, that should HorDcm Ratio of horizontal decimation. A number of HorDcm pixels will be dropped out of every consecutive 64 pixels in an input line. HorDcm/64 is the horizontal decimation factor. Ratio of vertical decimation. A number of VerDcm pixels will be dropped out of every consecutive 64 lines in an input field. VerDcm/64 is the vertical decimation factor. The horizontal filter through which the input is passed. The filter is selected according to the horizontal decimation factor that is first determined. VerDcm HFilter 46 Enhanced PCI Bus Multimedia Controller VSYNC VStart' VEnd' VStart VEnd floor or ceil (Ht/s) HEnd' HStart' Wa HStart HSYNC Ha/2 HEnd hcrop1 vcrop1 hcrop2 Total size of one input field Active portion of one input field The effective portion taken by the ZR36120 according to the programmed parameters. (The effective portion can be the entire active field or any partial sub-section of it). Figure 17. Input Image Parameters Calculating the Horizontal Parameters: X and We denote two temporary variables: X = ceil (VidWinWid*64/Wa) We = floor (VidWinWid*64/X) HorDcm = 64 - X hcrop1 = 2*floor((Wa-We)/4) hcrop2 = Wa - We - hcrop1 HStart and Hend are then calculated from hcrop1 and hcrop2. In the example: X = ceil(597*64/720) = 54 We = floor(597*64/54) = 707 HorDcm= 64 - 54 = 10 hcrop1 = 2*floor((720-707)/4) = 6 hcrop2 = 720-707 - 6 = 7 HStart = HStart' + hcrop1 = 122 + 6 = 128 HEnd = HEnd' - hcrop2 = 841 - 7 = 834 (834 - 128 + 1 = 707) The ZR36057 will actually sample-in 707 pixels from every line. The first 6 and the last 7 active pixels will be cut out. Calculating the Vertical Parameters (Regardless of DispMod!) Y and He denote two temporary variables: Y = ceil (VidWinHt*64*2/Ha) He = floor (VidWinHt*64/Y) VerDcm = 64 - Y vcrop1 = floor((Ha/2 - He)/2) vcrop2 = Ha/2 - He - vcrop1 VStart and VEnd are then calculated from vcrop1 and vcrop2. In the example: Y = ceil(199*64*2/480) = 54 He = floor(199*64/54) = 235 VerDcm= 64 - 54 = 10 vcrop1 = floor(((480/2) - 235) / 2) = 2 vcrop2 = (480/2) - 235 - 2 = 3 VStart = VStart' + vcrop1 = 10 + 2 = 12 VEnd = VEnd' - vcrop2 = 249 - 3 = 246 (246 - 12 + 1 = 235) The ZR36057 will actually sample-in 235 lines from every field. The first 2 and the last 3 active lines of every field will be cut out. 47 vcrop2 Enhanced PCI Bus Multimedia Controller ORDERING INFORMATION ZR 36057 PQ C PACKAGE PQ - Plastic Quad Flat Pack (EIAJ) SCREENING KEY PACKAGE PART NUMBER PREFIX SCREENING KEY C - 0C to +70C (VCC = 4.75V to 5.25V) SALES OFFICES T U.S. Headquarters Zoran Corporation 2041 Mission College Blvd Santa Clara, CA 95054 USA Telephone: 408-986-1314 FAX: 408-986-1240 T Israel Operations Zoran Microelectronics, Ltd. Advanced Technology Center P.O. Box 2495 Haifa, 31024 Israel Telephone: 972-4-8545-777 FAX: 972-4-8551-550 Trademarks: All brand, product, and company names are trademarks or registered trademarks of their respective companies. The material in this data sheet is for information only. Zoran Corporation assumes no responsibility for errors or omissions and reserves the right to change, without notice, product specifications, operating characteristics, packaging, etc. Zoran Corporation assumes no liability for damage resulting from the use of information contained in this document. DS36057-0896 |
Price & Availability of ZR36057
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |